Rom... CRC: len=0xf080, cal=0x27ff5de9, img=0x27ff5de9, match! Loading from boot device SPI NOR Header: 000|0x23ffdc0: 01 02 FF FF 4C 46 43 53 00 04 00 00 10 FB 05 00 010|0x23ffdd0: 01 04 FF FF 4C 46 43 53 00 00 06 00 D8 92 00 00 020|0x23ffde0: 01 03 FF FF 4C 46 43 53 00 00 07 00 15 8E 00 00 030|0x23ffdf0: 01 05 FF FF 4C 46 43 53 00 00 08 00 00 00 0B 01 040|0x23ffe00: 01 06 FF FF 4C 46 43 53 00 00 13 01 FD 17 00 00 050|0x23ffe10: 01 14 FF FF 4C 46 43 53 00 00 14 01 8C 3E 00 00 060|0x23ffe20: 7F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 070|0x23ffe30: 7F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 080|0x23ffe40: 7F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 090|0x23ffe50: 7F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0A0|0x23ffe60: 7F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0B0|0x23ffe70: 01 16 FF FF 4C 46 43 53 00 00 15 01 00 00 0A 00 0C0|0x23ffe80: 01 07 FF FF 4C 46 43 53 00 00 1F 01 E0 3D 1B 00 0D0|0x23ffe90: 7F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0E0|0x23ffea0: 7F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0F0|0x23ffeb0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 100|0x23ffec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 110|0x23ffed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 120|0x23ffee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 130|0x23ffef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 140|0x23fff00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 150|0x23fff10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 160|0x23fff20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 170|0x23fff30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 180|0x23fff40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 190|0x23fff50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1A0|0x23fff60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1B0|0x23fff70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1C0|0x23fff80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1D0|0x23fff90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1E0|0x23fffa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1F0|0x23fffb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Loading Normal Image from table offset 400 CRC: len=0x5fb10, cal=0x1352ae58, img=0x1352ae58, match! Jump to Boot1 @0x2200000 ===================== Cavium CN99XX BOOT1 ===================== Version : TX2-FW-Release-7.3-build_01 Built at 16:20:32 on Aug 13 2020 ===================== SPI NOR device inform: node=0, cs=0, khz=0 Chip Selection : 0 Device Name : Manufacturer : 0x20, MICRON ID Codes : 0xba20, 0x1044 Bytes Per Page : 0x100 Page Per Sector : 0x100 Total Sectors : 0x400 OTP: Freq: core 2199, mem 2199, socn 666, socs 1199 Power on reset config register: 0xffa7108 USB PPC Policy: 0 Slow Timer: 0 Ate Mode: 0 Boot Debug: 0 Run BIST: 1 PCI Mode: 7f PCI GangMode D: 1 PCI GangMode C: 2 PCI GangMode B: 3 PCI GangMode A: 4 Node ID: 0 PLL Freq: 0 Boot Device: 8 CPU MBIST: 0x00000000 (1 bit per cpu) CPU00: Pass CPU01: Pass CPU02: Pass CPU03: Pass CPU04: Pass CPU05: Pass CPU06: Pass CPU07: Pass CPU08: Pass CPU09: Pass CPU10: Pass CPU11: Pass CPU12: Pass CPU13: Pass CPU14: Pass CPU15: Pass CPU16: Pass CPU17: Pass CPU18: Pass CPU19: Pass CPU20: Pass CPU21: Pass CPU22: Pass CPU23: Pass CPU24: Pass CPU25: Pass CPU26: Pass CPU27: Pass CPU28: Pass CPU29: Pass CPU30: Pass CPU31: Pass BLK MBIST: 0x00000002 (1 bit per chain) MBIST_SYS: Pass MBIST_DMCL: Pass MBIST_DMCR: Pass MBIST_ICS_0: Pass MBIST_ICS_1: Pass MBIST_MEMB: Pass MBIST_PCIE_0: Pass MBIST_PCIE_1: Pass MBIST_PCIE_2: Pass MBIST_PCIE_3: Pass MBIST_SATA: Pass MBIST_USB: Pass MBIST_SOCN: Pass MBIST_SOCS: Pass MBIST_GIC: Pass MBIST_MEMT0: Pass MBIST_MEMT1: Pass MBIST_MEMT2: Pass MBIST_MEMT3: Pass MBIST_MEMT4: Pass MBIST_MEMT5: Pass MBIST_MEMT6: Pass MBIST_MEMT7: Pass Measuring FDT 0x225fb18-0x2261315 to PCR1 Board details from FDT: Name: Saber SD/MMC slot property not found sata@0: okay sata@1: okay usb@0: okay usb@1: okay PID:ISL68144X ADDR:0x47 CUSTOM_INFO:0x1 M3_HEARTBEAT_GPIO not found M3_HEARTBEAT_GPIO : -1 sata@0: disabled sata@1: disabled usb@0: okay usb@1: okay PID:ISL68144X ADDR:0x52 CUSTOM_INFO:0x1 M3_HEARTBEAT_GPIO not found M3_HEARTBEAT_GPIO : -1 Board FDT loaded Node 0 ICI links: Node 0 Link 0, data rate: 25 Gbps Node 0 Link 1, data rate: 25 Gbps Node 0 Link 2, data rate: 25 Gbps Node 0 Link 3, data rate: 25 Gbps Node 0 Link 4, data rate: 25 Gbps Node 0 Link 5, data rate: 25 Gbps Node 1 ICI links: Node 1 Link 0, data rate: 25 Gbps Node 1 Link 1, data rate: 25 Gbps Node 1 Link 2, data rate: 25 Gbps Node 1 Link 3, data rate: 25 Gbps Node 1 Link 4, data rate: 25 Gbps Node 1 Link 5, data rate: 25 Gbps Node 2 ICI links: Node 2 Link 0, data rate: 25 Gbps Node 2 Link 1, data rate: 25 Gbps Node 2 Link 2, data rate: 25 Gbps Node 2 Link 3, data rate: 25 Gbps Node 2 Link 4, data rate: 25 Gbps Node 2 Link 5, data rate: 25 Gbps Node 3 ICI links: Node 3 Link 0, data rate: 25 Gbps Node 3 Link 1, data rate: 25 Gbps Node 3 Link 2, data rate: 25 Gbps Node 3 Link 3, data rate: 25 Gbps Node 3 Link 4, data rate: 25 Gbps Node 3 Link 5, data rate: 25 Gbps Node 0 ICI Link Status Table: Link 0 1 2 3 4 5 Status Up Up Up Up Up Up ICI [node_0, link_0] connected to [peer_node_1, peer_link_5] ICI New node found in Discovery ICI [node_0, link_1] connected to [peer_node_1, peer_link_4] ICI [node_0, link_2] connected to [peer_node_1, peer_link_3] ICI [node_0, link_3] connected to [peer_node_1, peer_link_2] ICI [node_0, link_4] connected to [peer_node_1, peer_link_1] ICI [node_0, link_5] connected to [peer_node_1, peer_link_0] ICI [node_1, link_0] connected to [peer_node_0, peer_link_5] ICI [node_1, link_1] connected to [peer_node_0, peer_link_4] ICI [node_1, link_2] connected to [peer_node_0, peer_link_3] ICI [node_1, link_3] connected to [peer_node_0, peer_link_2] ICI [node_1, link_4] connected to [peer_node_0, peer_link_1] ICI [node_1, link_5] connected to [peer_node_0, peer_link_0] Node 1 ICI Link Status Table: Link 0 1 2 3 4 5 Status Up Up Up Up Up Up ICI Discovery complete: 2 nodes Slave Node, ID: 1 Disabling ICI intf.; Enabling GPIO mode ===================== GIGABYTE Information ===================== Project Name : MT91-FS4 BIOS Version : F34 ===================== Disabling SD/MMC0 intf.; Enabling GPIO mode Disabling SD/MMC0 intf.; Enabling GPIO mode Disabling SD/MMC0 intf.; Enabling GPIO mode Disabling SD/MMC0 intf.; Enabling GPIO mode Disabling SD/MMC0 intf.; Enabling GPIO mode Disabling SD/MMC0 intf.; Enabling GPIO mode Disabling SD/MMC0 intf.; Enabling GPIO mode Disabling SD/MMC0 intf.; Enabling GPIO mode Disabling SD/MMC0 intf.; Enabling GPIO mode Disabling SD/MMC0 intf.; Enabling GPIO mode Disabling PCIE intf.; Enabling GPIO mode Disabling PCIE intf.; Enabling GPIO mode Disabling ICI intf.; Enabling GPIO mode HOST_SMBUS Status=1 DDR_HOST_SMB Status=0 VR_PMB Status=1 PowerCTL1 Status=1 PowerCTL2 Status=1 PowerCTL3 Status=0 PowerCTL4 Status=0 Send_Reset_Request_BMC Status=1 RST_PCIE_CPU0_N Status=1 RST_PCIE_CPU1_N Status=1 GPIO_64 Status=1 GPIO_65 Status=1 PowerCTL I2C device Information: Clock (KHz) : 100 Trans Timeout : ffff Last Opr node : 0 Last Opr bus : 0 Press 's' to enter shell. Starting autoboot in : 0 Socket 0 CPU PART_ID 0x000020D9_20EB3296 Socket 1 CPU PART_ID 0x000020D9_28EB320A DDR4: DIMM_A0: RDIMM, ECC 2Rx8 HMA82GR7AFR8N-VK mfg:AD80.00 reg:3286.A0 s/n: 1119197304 1.2V DIMM_A1 DIMM not inserted, skipping N:0 C:0 ( DIMM_A0 ): DDR4: Mem size = 16384 MB RDIMM DDR4: DIMM_B0: RDIMM, ECC 2Rx8 HMA82GR7AFR8N-VK mfg:AD80.00 reg:3286.A0 s/n: 2192005422 1.2V DIMM_B1 DIMM not inserted, skipping N:0 C:1 ( DIMM_B0 ): DDR4: Mem size = 16384 MB RDIMM DDR4: DIMM_C0: RDIMM, ECC 1Rx4 HMA82GR7AFR4N-VK mfg:AD80.00 reg:B380.51 s/n: 1113284072 1.2V DIMM_C1 DIMM not inserted, skipping N:0 C:2 ( DIMM_C0 ): DDR4: Mem size = 16384 MB RDIMM DDR4: DIMM_D0: RDIMM, ECC 1Rx4 HMA82GR7AFR4N-VK mfg:AD80.00 reg:B380.51 s/n: 1113284090 1.2V DIMM_D1 DIMM not inserted, skipping N:0 C:3 ( DIMM_D0 ): DDR4: Mem size = 16384 MB RDIMM DIMM_E0 DIMM not inserted, skipping DIMM_F0 DIMM not inserted, skipping DIMM_G0 DIMM not inserted, skipping DIMM_H0 DIMM not inserted, skipping DDR4: DIMM_I0: RDIMM, ECC 2Rx8 HMA82GR7AFR8N-VK mfg:AD80.00 reg:3286.A0 s/n: 2191737438 1.2V DIMM_I1 DIMM not inserted, skipping N:1 C:0 ( DIMM_I0 ): DDR4: Mem size = 16384 MB RDIMM DDR4: DIMM_J0: RDIMM, ECC 2Rx8 HMA82GR7AFR8N-VK mfg:AD80.00 reg:3286.A0 s/n: 1119197356 1.2V DIMM_J1 DIMM not inserted, skipping N:1 C:1 ( DIMM_J0 ): DDR4: Mem size = 16384 MB RDIMM DDR4: DIMM_K0: RDIMM, ECC 1Rx4 HMA82GR7AFR4N-VK mfg:AD80.00 reg:B380.51 s/n: 1385075306 1.2V DIMM_K1 DIMM not inserted, skipping N:1 C:2 ( DIMM_K0 ): DDR4: Mem size = 16384 MB RDIMM DDR4: DIMM_L0: RDIMM, ECC 1Rx4 HMA82GR7AFR4N-VK mfg:AD80.00 reg:3286.A0 s/n: 1391183626 1.2V DIMM_L1 DIMM not inserted, skipping N:1 C:3 ( DIMM_L0 ): DDR4: Mem size = 16384 MB RDIMM DIMM_M0 DIMM not inserted, skipping DIMM_N0 DIMM not inserted, skipping DIMM_O0 DIMM not inserted, skipping DIMM_P0 DIMM not inserted, skipping DMCR PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 31 (181 PS) (48% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 39 (228 PS) (60% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 40 (234 PS) (62% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 36 (211 PS) (56% UI) DMCL PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 31 (181 PS) (48% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 41 (240 PS) (64% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 30 (176 PS) (46% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 40 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 39 (228 PS) (60% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 39 (702 mv) group 0 [C0.W 31 (48% UI)] [C2.W 33 (51% UI)] common 32 (49% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 40 (720 mv) group 0 [C0.W 39 (60% UI)] [C2.W 38 (59% UI)] common 39 (60% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 41 (738 mv) group 0 [C0.W 46 (71% UI)] [C2.W 43 (67% UI)] common 45 (70% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 42 (756 mv) group 0 [C0.W 46 (71% UI)] [C2.W 44 (68% UI)] common 45 (70% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 43 (774 mv) group 0 [C0.W 44 (68% UI)] [C2.W 45 (70% UI)] common 45 (70% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 44 (792 mv) group 0 [C0.W 40 (62% UI)] [C2.W 44 (68% UI)] common 42 (65% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 45 (810 mv) group 0 [C0.W 36 (56% UI)] [C2.W 40 (62% UI)] common 38 (59% UI) N:0 C:2 - N:0 C:0 : RL COMMON VREF [41, 41, 41, 41] eye [45, 45, 45, 45] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:0 C:0 ( DIMM_A0 ): ::_4::dmc soft reset number 1 requested... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ DMCR PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 32 (187 PS) (49% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 39 (228 PS) (60% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 36 (211 PS) (56% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 33 (193 PS) (51% UI) DMCL PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 30 (176 PS) (46% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 41 (240 PS) (64% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 30 (176 PS) (46% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 40 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 41 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 39 (228 PS) (60% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 36 (211 PS) (56% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 39 (702 mv) group 0 [C0.W 32 (49% UI)] [C2.W 33 (51% UI)] common 33 (51% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 40 (720 mv) group 0 [C0.W 37 (57% UI)] [C2.W 38 (59% UI)] common 38 (59% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 41 (738 mv) group 0 [C0.W 44 (68% UI)] [C2.W 40 (62% UI)] common 42 (65% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 42 (756 mv) group 0 [C0.W 44 (68% UI)] [C2.W 42 (65% UI)] common 43 (67% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 43 (774 mv) group 0 [C0.W 39 (60% UI)] [C2.W 41 (64% UI)] common 40 (62% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 44 (792 mv) group 0 [C0.W 36 (56% UI)] [C2.W 39 (60% UI)] common 38 (59% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 45 (810 mv) group 0 [C0.W 33 (51% UI)] [C2.W 37 (57% UI)] common 35 (54% UI) N:0 C:2 - N:0 C:0 : RL COMMON VREF [42, 42, 42, 42] eye [43, 43, 43, 43] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:0 C:0 ( DIMM_A0 ): ::_4::dmc soft reset number 2 requested... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ DMCR PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 31 (181 PS) (48% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 38 (222 PS) (59% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 40 (234 PS) (62% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:0 ( DIMM_A0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 32 (187 PS) (49% UI) DMCL PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 30 (176 PS) (46% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 35 (205 PS) (54% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 41 (240 PS) (64% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 29 (170 PS) (45% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 48 (281 PS) (74% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 47 (275 PS) (73% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 39 (702 mv) group 0 [C0.W 31 (48% UI)] [C2.W 33 (51% UI)] common 32 (49% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 40 (720 mv) group 0 [C0.W 38 (59% UI)] [C2.W 38 (59% UI)] common 38 (59% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 41 (738 mv) group 0 [C0.W 44 (68% UI)] [C2.W 43 (67% UI)] common 44 (68% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 42 (756 mv) group 0 [C0.W 43 (67% UI)] [C2.W 48 (74% UI)] common 46 (71% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 43 (774 mv) group 0 [C0.W 40 (62% UI)] [C2.W 47 (73% UI)] common 44 (68% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 44 (792 mv) group 0 [C0.W 37 (57% UI)] [C2.W 45 (70% UI)] common 41 (64% UI) N:0 C:0 ( DIMM_A0 ): soc_vref_dq 45 (810 mv) group 0 [C0.W 32 (49% UI)] [C2.W 43 (67% UI)] common 38 (59% UI) N:0 C:2 - N:0 C:0 : RL COMMON VREF [42, 42, 42, 42] eye [46, 46, 46, 46] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:0 C:0 ::_4::Final Read Level Failure... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ N:0 C:0 ( ): Final RL: soc_vref 42 eye_width 9 (13% UI) N:0 C:2 ( DIMM_C0 ): Final RL: soc_vref 42 eye_width 47 (73% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 16 eye_width 0x37 (322 PS) (85% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 17 eye_width 0x37 (322 PS) (85% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 18 eye_width 0x34 (305 PS) (81% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 19 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 20 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 21 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 22 eye_width 0x32 (293 PS) (78% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 23 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 25 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 26 eye_width 0x2e (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 27 eye_width 0x2e (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 28 eye_width 0x2c (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 29 eye_width 0x2c (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 30 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 31 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 33 eye_width 0x28 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 34 eye_width 0x27 (228 PS) (60% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 35 eye_width 0x25 (217 PS) (57% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 36 eye_width 0x22 (199 PS) (53% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 37 eye_width 0x21 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 38 eye_width 0x21 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 39 eye_width 0x1e (176 PS) (46% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 40 eye_width 0x1d (170 PS) (45% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 41 eye_width 0x1a (152 PS) (40% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 42 eye_width 0x15 (123 PS) (32% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 43 eye_width 0x12 (105 PS) (28% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 44 eye_width 0x0d (76 PS) (20% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 45 eye_width 0x0b (64 PS) (17% UI) N:0 C:2 ( DIMM_C0 ): WL: check if write vREF 16 is optimized choice N:0 C:2 ( DIMM_C0 ): WL: eye-- 751 eye- 0 eye 85 eye+ 85 eye++ 81 N:0 C:2 ( DIMM_C0 ): WL: final write vREF 16 N:0 C:2 ( DIMM_C0 ): Final WL: 1: dram_vref_dq 16 eye_width 0x37 (322 ps) (85% UI) N:0 C:2 ( DIMM_C0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 31 (181 PS) (48% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 36 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 49 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 39 (702 mv) group 0 [C1.W 30 (46% UI)] [C3.W 31 (48% UI)] common 31 (48% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 40 (720 mv) group 0 [C1.W 35 (54% UI)] [C3.W 36 (56% UI)] common 36 (56% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 41 (738 mv) group 0 [C1.W 44 (68% UI)] [C3.W 42 (65% UI)] common 43 (67% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 42 (756 mv) group 0 [C1.W 41 (64% UI)] [C3.W 45 (70% UI)] common 43 (67% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 43 (774 mv) group 0 [C1.W 37 (57% UI)] [C3.W 49 (76% UI)] common 43 (67% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 44 (792 mv) group 0 [C1.W 33 (51% UI)] [C3.W 46 (71% UI)] common 40 (62% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 45 (810 mv) group 0 [C1.W 29 (45% UI)] [C3.W 44 (68% UI)] common 37 (57% UI) N:0 C:3 - N:0 C:1 : RL COMMON VREF [41, 41, 41, 41] eye [43, 43, 43, 43] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:0 C:1 ( DIMM_B0 ): ::_4::dmc soft reset number 1 requested... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ DMCL PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 28 (164 PS) (43% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 35 (205 PS) (54% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 41 (240 PS) (64% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 29 (170 PS) (45% UI) DMCR PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 40 (234 PS) (62% UI) Peak VREF [42, 42, 42, 42] eye [46, 46, 46, 46] N:0 C:2 ( DIMM_C0 ): Final RL: group 0 soc_vref 42 eye_width 47 73% N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 16 eye_width 0x38 (328 PS) (87% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 17 eye_width 0x38 (328 PS) (87% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 18 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 19 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 20 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 21 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 22 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 23 eye_width 0x32 (293 PS) (78% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 25 eye_width 0x32 (293 PS) (78% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 26 eye_width 0x2f (275 PS) (73% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 27 eye_width 0x2d (264 PS) (70% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 28 eye_width 0x2c (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 29 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 30 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 31 eye_width 0x29 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 33 eye_width 0x28 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 35 eye_width 0x25 (217 PS) (57% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 36 eye_width 0x22 (199 PS) (53% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 37 eye_width 0x21 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 38 eye_width 0x1e (176 PS) (46% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 39 eye_width 0x1d (170 PS) (45% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 40 eye_width 0x1a (152 PS) (40% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 41 eye_width 0x19 (146 PS) (38% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 42 eye_width 0x16 (129 PS) (34% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 43 eye_width 0x11 (99 PS) (26% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 44 eye_width 0x0e (82 PS) (21% UI) N:0 C:2 ( DIMM_C0 ): WL 0: dram_vref_dq 45 eye_width 0x11 (99 PS) (26% UI) N:0 C:2 ( DIMM_C0 ): WL: check if write vREF 16 is optimized choice N:0 C:2 ( DIMM_C0 ): WL: eye-- 751 eye- 0 eye 87 eye+ 87 eye++ 82 N:0 C:2 ( DIMM_C0 ): WL: final write vREF 16 N:0 C:2 ( DIMM_C0 ): Final WL: 1: dram_vref_dq 16 eye_width 0x38 (328 ps) (87% UI) N:0 C:2 ( DIMM_C0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 31 (181 PS) (48% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 36 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 49 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 48 (281 PS) (74% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 39 (702 mv) group 0 [C1.W 28 (43% UI)] [C3.W 31 (48% UI)] common 30 (46% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 40 (720 mv) group 0 [C1.W 35 (54% UI)] [C3.W 36 (56% UI)] common 36 (56% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 41 (738 mv) group 0 [C1.W 43 (67% UI)] [C3.W 42 (65% UI)] common 43 (67% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 42 (756 mv) group 0 [C1.W 41 (64% UI)] [C3.W 46 (71% UI)] common 44 (68% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 43 (774 mv) group 0 [C1.W 37 (57% UI)] [C3.W 49 (76% UI)] common 43 (67% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 44 (792 mv) group 0 [C1.W 33 (51% UI)] [C3.W 48 (74% UI)] common 41 (64% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 45 (810 mv) group 0 [C1.W 29 (45% UI)] [C3.W 45 (70% UI)] common 37 (57% UI) N:0 C:3 - N:0 C:1 : RL COMMON VREF [42, 42, 42, 42] eye [44, 44, 44, 44] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:0 C:1 ( DIMM_B0 ): ::_4::dmc soft reset number 2 requested... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ DMCL PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 28 (164 PS) (43% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 35 (205 PS) (54% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 41 (240 PS) (64% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 41 (240 PS) (64% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:1 ( DIMM_B0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 30 (176 PS) (46% UI) DMCR PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 40 (234 PS) (62% UI) Peak VREF [42, 42, 42, 42] eye [46, 46, 46, 46] N:0 C:2 ( DIMM_C0 ): Final RL: group 0 soc_vref 42 eye_width 47 73% N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 16 eye_width 0x37 (322 PS) (85% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 17 eye_width 0x34 (305 PS) (81% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 18 eye_width 0x34 (305 PS) (81% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 19 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 20 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 21 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 22 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 23 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 25 eye_width 0x2f (275 PS) (73% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 26 eye_width 0x2e (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 27 eye_width 0x2e (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 28 eye_width 0x2d (264 PS) (70% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 29 eye_width 0x2c (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 30 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 31 eye_width 0x29 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 32 eye_width 0x28 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 33 eye_width 0x28 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 35 eye_width 0x25 (217 PS) (57% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 36 eye_width 0x23 (205 PS) (54% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 37 eye_width 0x21 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 38 eye_width 0x1e (176 PS) (46% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 39 eye_width 0x1f (181 PS) (48% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 40 eye_width 0x1c (164 PS) (43% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 41 eye_width 0x18 (140 PS) (37% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 42 eye_width 0x15 (123 PS) (32% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 43 eye_width 0x11 (99 PS) (26% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 44 eye_width 0x0f (88 PS) (23% UI) N:0 C:2 ( DIMM_C0 ): WL 0: dram_vref_dq 45 eye_width 0x12 (105 PS) (28% UI) N:0 C:2 ( DIMM_C0 ): WL: check if write vREF 16 is optimized choice N:0 C:2 ( DIMM_C0 ): WL: eye-- 751 eye- 0 eye 85 eye+ 81 eye++ 81 N:0 C:2 ( DIMM_C0 ): WL: final write vREF 16 N:0 C:2 ( DIMM_C0 ): Final WL: 1: dram_vref_dq 16 eye_width 0x38 (328 ps) (87% UI) N:0 C:2 ( DIMM_C0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 31 (181 PS) (48% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 37 (217 PS) (57% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 48 (281 PS) (74% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 47 (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 39 (702 mv) group 0 [C1.W 28 (43% UI)] [C3.W 31 (48% UI)] common 30 (46% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 40 (720 mv) group 0 [C1.W 35 (54% UI)] [C3.W 37 (57% UI)] common 36 (56% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 41 (738 mv) group 0 [C1.W 41 (64% UI)] [C3.W 42 (65% UI)] common 42 (65% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 42 (756 mv) group 0 [C1.W 41 (64% UI)] [C3.W 46 (71% UI)] common 44 (68% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 43 (774 mv) group 0 [C1.W 37 (57% UI)] [C3.W 48 (74% UI)] common 43 (67% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 44 (792 mv) group 0 [C1.W 33 (51% UI)] [C3.W 47 (73% UI)] common 40 (62% UI) N:0 C:1 ( DIMM_B0 ): soc_vref_dq 45 (810 mv) group 0 [C1.W 30 (46% UI)] [C3.W 44 (68% UI)] common 37 (57% UI) N:0 C:3 - N:0 C:1 : RL COMMON VREF [42, 42, 42, 42] eye [44, 44, 44, 44] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:0 C:1 ::_4::Final Read Level Failure... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ N:0 C:1 ( ): Final RL: soc_vref 42 eye_width 11 (17% UI) N:0 C:3 ( DIMM_D0 ): Final RL: soc_vref 42 eye_width 46 (71% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 16 eye_width 0x36 (316 PS) (84% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 17 eye_width 0x37 (322 PS) (85% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 18 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 19 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 20 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 21 eye_width 0x32 (293 PS) (78% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 22 eye_width 0x33 (299 PS) (79% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 23 eye_width 0x31 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 25 eye_width 0x30 (281 PS) (74% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 26 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 27 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 28 eye_width 0x2d (264 PS) (70% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 29 eye_width 0x2b (252 PS) (67% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 30 eye_width 0x2c (258 PS) (68% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 31 eye_width 0x29 (240 PS) (64% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 33 eye_width 0x27 (228 PS) (60% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 35 eye_width 0x24 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 36 eye_width 0x23 (205 PS) (54% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 37 eye_width 0x22 (199 PS) (53% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 38 eye_width 0x20 (187 PS) (49% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 39 eye_width 0x1e (176 PS) (46% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 40 eye_width 0x1c (164 PS) (43% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 41 eye_width 0x1a (152 PS) (40% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 42 eye_width 0x17 (134 PS) (35% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 43 eye_width 0x15 (123 PS) (32% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 44 eye_width 0x13 (111 PS) (29% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 45 eye_width 0x0e (82 PS) (21% UI) N:0 C:3 ( DIMM_D0 ): WL: check if write vREF 18 is optimized choice N:0 C:3 ( DIMM_D0 ): WL: eye-- 84 eye- 85 eye 87 eye+ 87 eye++ 87 N:0 C:3 ( DIMM_D0 ): WL: final write vREF 18 N:0 C:3 ( DIMM_D0 ): Final WL: 1: dram_vref_dq 18 eye_width 0x38 (328 ps) (87% UI) N:0 C:3 ( DIMM_D0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 DMCR PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 25 (146 PS) (38% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 42 (246 PS) (65% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 39 (228 PS) (60% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 35 (205 PS) (54% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 29 (170 PS) (45% UI) DMCL PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 46 (269 PS) (71% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 44 (258 PS) (68% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 41 (240 PS) (64% UI) N:1 C:1 ( DIMM_J0 ): RL 0: soc_vref_dq 50 (900 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 33 (193 PS) (51% UI) N:1 C:1 ( DIMM_J0 ): Discontinuity in read leveling detected, restarting training N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 43 (252 PS) (67% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 48 (281 PS) (74% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 50 (293 PS) (78% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 48 (281 PS) (74% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 46 (269 PS) (71% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 44 (258 PS) (68% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 39 (702 mv) group 0 [C0.W 25 (38% UI)] [C2.W 32 (49% UI)] common 29 (45% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 40 (720 mv) group 0 [C0.W 32 (49% UI)] [C2.W 38 (59% UI)] common 35 (54% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 41 (738 mv) group 0 [C0.W 38 (59% UI)] [C2.W 43 (67% UI)] common 41 (64% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 42 (756 mv) group 0 [C0.W 42 (65% UI)] [C2.W 48 (74% UI)] common 45 (70% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 43 (774 mv) group 0 [C0.W 39 (60% UI)] [C2.W 50 (78% UI)] common 45 (70% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 44 (792 mv) group 0 [C0.W 35 (54% UI)] [C2.W 48 (74% UI)] common 42 (65% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 45 (810 mv) group 0 [C0.W 29 (45% UI)] [C2.W 46 (71% UI)] common 38 (59% UI) N:1 C:2 - N:1 C:0 : RL COMMON VREF [42, 42, 42, 42] eye [45, 45, 45, 45] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:1 C:0 ( DIMM_I0 ): ::_4::dmc soft reset number 1 requested... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ DMCR PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 33 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 41 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 41 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 39 (228 PS) (60% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 38 (222 PS) (59% UI) Peak VREF [42, 42, 42, 42] eye [43, 43, 43, 43] N:0 C:2 ( DIMM_C0 ): Final RL: group 0 soc_vref 42 eye_width 43 67% N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 16 eye_width 0x37 (322 PS) (85% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 17 eye_width 0x37 (322 PS) (85% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 18 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 19 eye_width 0x37 (322 PS) (85% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 20 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 21 eye_width 0x34 (305 PS) (81% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 22 eye_width 0x34 (305 PS) (81% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 23 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 25 eye_width 0x30 (281 PS) (74% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 26 eye_width 0x2e (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 27 eye_width 0x2e (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 28 eye_width 0x2d (264 PS) (70% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 29 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 30 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 31 eye_width 0x29 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 33 eye_width 0x28 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 34 eye_width 0x27 (228 PS) (60% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 35 eye_width 0x25 (217 PS) (57% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 36 eye_width 0x21 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 37 eye_width 0x22 (199 PS) (53% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 38 eye_width 0x1e (176 PS) (46% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 39 eye_width 0x1c (164 PS) (43% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 40 eye_width 0x1c (164 PS) (43% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 41 eye_width 0x18 (140 PS) (37% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 42 eye_width 0x15 (123 PS) (32% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 43 eye_width 0x11 (99 PS) (26% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 44 eye_width 0x0e (82 PS) (21% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 45 eye_width 0x09 (52 PS) (13% UI) N:0 C:2 ( DIMM_C0 ): WL: check if write vREF 16 is optimized choice N:0 C:2 ( DIMM_C0 ): WL: eye-- 751 eye- 0 eye 85 eye+ 85 eye++ 82 N:0 C:2 ( DIMM_C0 ): WL: write vREF needed optimization to right 17 N:0 C:2 ( DIMM_C0 ): WL: final write vREF 17 N:0 C:2 ( DIMM_C0 ): Final WL: 1: dram_vref_dq 17 eye_width 0x37 (322 ps) (85% UI) N:0 C:2 ( DIMM_C0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 DMCL PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 31 (181 PS) (48% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 36 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 49 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 47 (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 43 (252 PS) (67% UI) Peak VREF [43, 43, 43, 43] eye [49, 49, 49, 49] N:0 C:3 ( DIMM_D0 ): Final RL: group 0 soc_vref 43 eye_width 49 76% N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 16 eye_width 0x36 (316 PS) (84% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 17 eye_width 0x37 (322 PS) (85% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 18 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 19 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 20 eye_width 0x37 (322 PS) (85% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 21 eye_width 0x33 (299 PS) (79% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 22 eye_width 0x33 (299 PS) (79% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 23 eye_width 0x31 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 25 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 26 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 27 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 28 eye_width 0x2e (269 PS) (71% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 29 eye_width 0x2c (258 PS) (68% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 30 eye_width 0x2c (258 PS) (68% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 31 eye_width 0x2a (246 PS) (65% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 33 eye_width 0x28 (234 PS) (62% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 35 eye_width 0x24 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 36 eye_width 0x22 (199 PS) (53% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 37 eye_width 0x22 (199 PS) (53% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 38 eye_width 0x20 (187 PS) (49% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 39 eye_width 0x1d (170 PS) (45% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 40 eye_width 0x1e (176 PS) (46% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 41 eye_width 0x1a (152 PS) (40% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 42 eye_width 0x18 (140 PS) (37% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 43 eye_width 0x15 (123 PS) (32% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 44 eye_width 0x13 (111 PS) (29% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 45 eye_width 0x0f (88 PS) (23% UI) N:0 C:3 ( DIMM_D0 ): WL: check if write vREF 18 is optimized choice N:0 C:3 ( DIMM_D0 ): WL: eye-- 84 eye- 85 eye 87 eye+ 87 eye++ 85 N:0 C:3 ( DIMM_D0 ): WL: final write vREF 18 N:0 C:3 ( DIMM_D0 ): Final WL: 1: dram_vref_dq 18 eye_width 0x38 (328 ps) (87% UI) N:0 C:3 ( DIMM_D0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 DMCR PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 26 (152 PS) (40% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 41 (240 PS) (64% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 37 (217 PS) (57% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 34 (199 PS) (53% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 29 (170 PS) (45% UI) DMCL PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 45 (264 PS) (70% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 42 (246 PS) (65% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:1 ( DIMM_J0 ): RL 0: soc_vref_dq 50 (900 mv) group 0 eye_width 37 (217 PS) (57% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 33 (193 PS) (51% UI) N:1 C:1 ( DIMM_J0 ): Discontinuity in read leveling detected, restarting training N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 37 (217 PS) (57% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 48 (281 PS) (74% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 49 (287 PS) (76% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 47 (275 PS) (73% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 45 (264 PS) (70% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 42 (246 PS) (65% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 39 (702 mv) group 0 [C0.W 26 (40% UI)] [C2.W 32 (49% UI)] common 29 (45% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 40 (720 mv) group 0 [C0.W 32 (49% UI)] [C2.W 37 (57% UI)] common 35 (54% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 41 (738 mv) group 0 [C0.W 38 (59% UI)] [C2.W 42 (65% UI)] common 40 (62% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 42 (756 mv) group 0 [C0.W 41 (64% UI)] [C2.W 48 (74% UI)] common 45 (70% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 43 (774 mv) group 0 [C0.W 37 (57% UI)] [C2.W 49 (76% UI)] common 43 (67% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 44 (792 mv) group 0 [C0.W 34 (53% UI)] [C2.W 47 (73% UI)] common 41 (64% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 45 (810 mv) group 0 [C0.W 29 (45% UI)] [C2.W 45 (70% UI)] common 37 (57% UI) N:1 C:2 - N:1 C:0 : RL COMMON VREF [42, 42, 42, 42] eye [45, 45, 45, 45] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:1 C:0 ( DIMM_I0 ): ::_4::dmc soft reset number 2 requested... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ DMCR PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 32 (187 PS) (49% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 41 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 39 (228 PS) (60% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 38 (222 PS) (59% UI) Peak VREF [42, 42, 42, 42] eye [43, 43, 43, 43] N:0 C:2 ( DIMM_C0 ): Final RL: group 0 soc_vref 42 eye_width 43 67% N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 16 eye_width 0x37 (322 PS) (85% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 17 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 18 eye_width 0x36 (316 PS) (84% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 19 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 20 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 21 eye_width 0x36 (316 PS) (84% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 22 eye_width 0x34 (305 PS) (81% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 23 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 25 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 26 eye_width 0x2f (275 PS) (73% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 27 eye_width 0x2f (275 PS) (73% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 28 eye_width 0x2d (264 PS) (70% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 29 eye_width 0x2c (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 30 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 31 eye_width 0x2a (246 PS) (65% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 32 eye_width 0x28 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 33 eye_width 0x27 (228 PS) (60% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 35 eye_width 0x25 (217 PS) (57% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 36 eye_width 0x22 (199 PS) (53% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 37 eye_width 0x21 (193 PS) (51% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 38 eye_width 0x1f (181 PS) (48% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 39 eye_width 0x1e (176 PS) (46% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 40 eye_width 0x1b (158 PS) (42% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 41 eye_width 0x19 (146 PS) (38% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 42 eye_width 0x16 (129 PS) (34% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 43 eye_width 0x12 (105 PS) (28% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 44 eye_width 0x0e (82 PS) (21% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 45 eye_width 0x0a (58 PS) (15% UI) N:0 C:2 ( DIMM_C0 ): WL: check if write vREF 16 is optimized choice N:0 C:2 ( DIMM_C0 ): WL: eye-- 751 eye- 0 eye 85 eye+ 82 eye++ 84 N:0 C:2 ( DIMM_C0 ): WL: final write vREF 16 N:0 C:2 ( DIMM_C0 ): Final WL: 1: dram_vref_dq 16 eye_width 0x37 (322 ps) (85% UI) N:0 C:2 ( DIMM_C0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 DMCL PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 31 (181 PS) (48% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 36 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 49 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 47 (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 42 (246 PS) (65% UI) Peak VREF [43, 43, 43, 43] eye [49, 49, 49, 49] N:0 C:3 ( DIMM_D0 ): Final RL: group 0 soc_vref 43 eye_width 49 76% N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 16 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 17 eye_width 0x37 (322 PS) (85% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 18 eye_width 0x39 (334 PS) (89% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 19 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 20 eye_width 0x39 (334 PS) (89% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 21 eye_width 0x33 (299 PS) (79% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 22 eye_width 0x31 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 23 eye_width 0x31 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 25 eye_width 0x30 (281 PS) (74% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 26 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 27 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 28 eye_width 0x2e (269 PS) (71% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 29 eye_width 0x2c (258 PS) (68% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 30 eye_width 0x2c (258 PS) (68% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 31 eye_width 0x2a (246 PS) (65% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 33 eye_width 0x28 (234 PS) (62% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 35 eye_width 0x24 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 36 eye_width 0x24 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 37 eye_width 0x22 (199 PS) (53% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 38 eye_width 0x22 (199 PS) (53% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 39 eye_width 0x1e (176 PS) (46% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 40 eye_width 0x1d (170 PS) (45% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 41 eye_width 0x1a (152 PS) (40% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 42 eye_width 0x18 (140 PS) (37% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 43 eye_width 0x15 (123 PS) (32% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 44 eye_width 0x13 (111 PS) (29% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 45 eye_width 0x0e (82 PS) (21% UI) N:0 C:3 ( DIMM_D0 ): WL: check if write vREF 18 is optimized choice N:0 C:3 ( DIMM_D0 ): WL: eye-- 87 eye- 85 eye 89 eye+ 87 eye++ 89 N:0 C:3 ( DIMM_D0 ): WL: write vREF needed optimization to right 19 N:0 C:3 ( DIMM_D0 ): WL: final write vREF 19 N:0 C:3 ( DIMM_D0 ): Final WL: 1: dram_vref_dq 19 eye_width 0x39 (334 ps) (89% UI) N:0 C:3 ( DIMM_D0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 DMCR PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 25 (146 PS) (38% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 42 (246 PS) (65% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:0 ( DIMM_I0 ): RL 1: soc_vref_dq 50 (900 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:0 ( DIMM_I0 ): RL 0: soc_vref_dq 51 (918 mv) group 0 eye_width 29 (170 PS) (45% UI) DMCL PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 45 (264 PS) (70% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 45 (264 PS) (70% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 41 (240 PS) (64% UI) N:1 C:1 ( DIMM_J0 ): RL 0: soc_vref_dq 50 (900 mv) group 0 eye_width 37 (217 PS) (57% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 33 (193 PS) (51% UI) N:1 C:1 ( DIMM_J0 ): Discontinuity in read leveling detected, restarting training N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 33 (193 PS) (51% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 48 (281 PS) (74% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 49 (287 PS) (76% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 47 (275 PS) (73% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 46 (269 PS) (71% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 43 (252 PS) (67% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 39 (702 mv) group 0 [C0.W 25 (38% UI)] [C2.W 33 (51% UI)] common 29 (45% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 40 (720 mv) group 0 [C0.W 32 (49% UI)] [C2.W 38 (59% UI)] common 35 (54% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 41 (738 mv) group 0 [C0.W 38 (59% UI)] [C2.W 42 (65% UI)] common 40 (62% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 42 (756 mv) group 0 [C0.W 42 (65% UI)] [C2.W 48 (74% UI)] common 45 (70% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 43 (774 mv) group 0 [C0.W 38 (59% UI)] [C2.W 49 (76% UI)] common 44 (68% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 44 (792 mv) group 0 [C0.W 32 (49% UI)] [C2.W 47 (73% UI)] common 40 (62% UI) N:1 C:0 ( DIMM_I0 ): soc_vref_dq 45 (810 mv) group 0 [C0.W 29 (45% UI)] [C2.W 46 (71% UI)] common 38 (59% UI) N:1 C:2 - N:1 C:0 : RL COMMON VREF [42, 42, 42, 42] eye [45, 45, 45, 45] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:1 C:0 ::_4::Final Read Level Failure... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ N:1 C:0 ( ): Final RL: soc_vref 42 eye_width 10 (15% UI) N:1 C:2 ( DIMM_K0 ): Final RL: soc_vref 42 eye_width 48 (74% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 16 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 17 eye_width 0x34 (305 PS) (81% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 18 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 19 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 20 eye_width 0x34 (305 PS) (81% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 21 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 22 eye_width 0x31 (287 PS) (76% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 23 eye_width 0x30 (281 PS) (74% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 24 eye_width 0x30 (281 PS) (74% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 25 eye_width 0x2f (275 PS) (73% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 26 eye_width 0x2e (269 PS) (71% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 27 eye_width 0x2c (258 PS) (68% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 28 eye_width 0x2b (252 PS) (67% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 29 eye_width 0x29 (240 PS) (64% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 30 eye_width 0x29 (240 PS) (64% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 31 eye_width 0x29 (240 PS) (64% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 33 eye_width 0x28 (234 PS) (62% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 34 eye_width 0x25 (217 PS) (57% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 35 eye_width 0x25 (217 PS) (57% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 36 eye_width 0x23 (205 PS) (54% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 37 eye_width 0x22 (199 PS) (53% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 38 eye_width 0x20 (187 PS) (49% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 39 eye_width 0x20 (187 PS) (49% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 40 eye_width 0x1e (176 PS) (46% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 41 eye_width 0x1c (164 PS) (43% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 42 eye_width 0x19 (146 PS) (38% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 43 eye_width 0x17 (134 PS) (35% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 44 eye_width 0x12 (105 PS) (28% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 45 eye_width 0x11 (99 PS) (26% UI) N:1 C:2 ( DIMM_K0 ): WL: check if write vREF 17 is optimized choice N:1 C:2 ( DIMM_K0 ): WL: eye-- 0 eye- 79 eye 81 eye+ 79 eye++ 79 N:1 C:2 ( DIMM_K0 ): WL: final write vREF 17 N:1 C:2 ( DIMM_K0 ): Final WL: 1: dram_vref_dq 17 eye_width 0x34 (305 ps) (81% UI) N:1 C:2 ( DIMM_K0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 33 (193 PS) (51% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 43 (252 PS) (67% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 48 (281 PS) (74% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 49 (287 PS) (76% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 46 (269 PS) (71% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 44 (258 PS) (68% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 41 (240 PS) (64% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 39 (702 mv) group 0 [C1.W 32 (49% UI)] [C3.W 33 (51% UI)] common 33 (51% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 40 (720 mv) group 0 [C1.W 38 (59% UI)] [C3.W 38 (59% UI)] common 38 (59% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 41 (738 mv) group 0 [C1.W 45 (70% UI)] [C3.W 43 (67% UI)] common 44 (68% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 42 (756 mv) group 0 [C1.W 45 (70% UI)] [C3.W 48 (74% UI)] common 47 (73% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 43 (774 mv) group 0 [C1.W 41 (64% UI)] [C3.W 49 (76% UI)] common 45 (70% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 44 (792 mv) group 0 [C1.W 37 (57% UI)] [C3.W 46 (71% UI)] common 42 (65% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 45 (810 mv) group 0 [C1.W 33 (51% UI)] [C3.W 44 (68% UI)] common 39 (60% UI) N:1 C:3 - N:1 C:1 : RL COMMON VREF [42, 42, 42, 42] eye [47, 47, 47, 47] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:1 C:1 ( DIMM_J0 ): ::_4::dmc soft reset number 1 requested... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ DMCR PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 32 (187 PS) (49% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 44 (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 40 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 38 (222 PS) (59% UI) Peak VREF [42, 42, 42, 42] eye [45, 45, 45, 45] N:0 C:2 ( DIMM_C0 ): Final RL: group 0 soc_vref 42 eye_width 44 68% N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 16 eye_width 0x38 (328 PS) (87% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 17 eye_width 0x36 (316 PS) (84% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 18 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 19 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 20 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 21 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 22 eye_width 0x34 (305 PS) (81% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 23 eye_width 0x32 (293 PS) (78% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 25 eye_width 0x30 (281 PS) (74% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 26 eye_width 0x2f (275 PS) (73% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 27 eye_width 0x2e (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 28 eye_width 0x2d (264 PS) (70% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 29 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 30 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 31 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 33 eye_width 0x28 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 35 eye_width 0x24 (211 PS) (56% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 36 eye_width 0x22 (199 PS) (53% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 37 eye_width 0x20 (187 PS) (49% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 38 eye_width 0x20 (187 PS) (49% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 39 eye_width 0x1d (170 PS) (45% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 40 eye_width 0x1c (164 PS) (43% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 41 eye_width 0x18 (140 PS) (37% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 42 eye_width 0x15 (123 PS) (32% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 43 eye_width 0x10 (93 PS) (24% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 44 eye_width 0x0d (76 PS) (20% UI) N:0 C:2 ( DIMM_C0 ): WL 0: dram_vref_dq 45 eye_width 0x12 (105 PS) (28% UI) N:0 C:2 ( DIMM_C0 ): WL: check if write vREF 16 is optimized choice N:0 C:2 ( DIMM_C0 ): WL: eye-- 751 eye- 0 eye 87 eye+ 84 eye++ 82 N:0 C:2 ( DIMM_C0 ): WL: final write vREF 16 N:0 C:2 ( DIMM_C0 ): Final WL: 1: dram_vref_dq 16 eye_width 0x38 (328 ps) (87% UI) N:0 C:2 ( DIMM_C0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 DMCL PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 31 (181 PS) (48% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 36 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 49 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 48 (281 PS) (74% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 42 (246 PS) (65% UI) Peak VREF [43, 43, 43, 43] eye [49, 49, 49, 49] N:0 C:3 ( DIMM_D0 ): Final RL: group 0 soc_vref 43 eye_width 48 74% N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 16 eye_width 0x37 (322 PS) (85% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 17 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 18 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 19 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 20 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 21 eye_width 0x33 (299 PS) (79% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 22 eye_width 0x33 (299 PS) (79% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 23 eye_width 0x32 (293 PS) (78% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 24 eye_width 0x30 (281 PS) (74% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 25 eye_width 0x31 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 26 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 27 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 28 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 29 eye_width 0x2c (258 PS) (68% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 30 eye_width 0x2c (258 PS) (68% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 31 eye_width 0x29 (240 PS) (64% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 32 eye_width 0x28 (234 PS) (62% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 33 eye_width 0x28 (234 PS) (62% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 35 eye_width 0x24 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 36 eye_width 0x22 (199 PS) (53% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 37 eye_width 0x22 (199 PS) (53% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 38 eye_width 0x20 (187 PS) (49% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 39 eye_width 0x1d (170 PS) (45% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 40 eye_width 0x1d (170 PS) (45% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 41 eye_width 0x1a (152 PS) (40% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 42 eye_width 0x17 (134 PS) (35% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 43 eye_width 0x15 (123 PS) (32% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 44 eye_width 0x13 (111 PS) (29% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 45 eye_width 0x0f (88 PS) (23% UI) N:0 C:3 ( DIMM_D0 ): WL: check if write vREF 17 is optimized choice N:0 C:3 ( DIMM_D0 ): WL: eye-- 0 eye- 85 eye 87 eye+ 87 eye++ 87 N:0 C:3 ( DIMM_D0 ): WL: final write vREF 17 N:0 C:3 ( DIMM_D0 ): Final WL: 1: dram_vref_dq 17 eye_width 0x37 (322 ps) (85% UI) N:0 C:3 ( DIMM_D0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 DMCL PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 39 (228 PS) (60% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 46 (269 PS) (71% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 44 (258 PS) (68% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 41 (240 PS) (64% UI) N:1 C:1 ( DIMM_J0 ): RL 0: soc_vref_dq 50 (900 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 33 (193 PS) (51% UI) N:1 C:1 ( DIMM_J0 ): Discontinuity in read leveling detected, restarting training DMCR PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 33 (193 PS) (51% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 37 (217 PS) (57% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 43 (252 PS) (67% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 47 (275 PS) (73% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 49 (287 PS) (76% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 46 (269 PS) (71% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 44 (258 PS) (68% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 42 (246 PS) (65% UI) Peak VREF [43, 43, 43, 43] eye [49, 49, 49, 49] N:1 C:2 ( DIMM_K0 ): Final RL: group 0 soc_vref 43 eye_width 48 74% N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 16 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 17 eye_width 0x34 (305 PS) (81% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 18 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 19 eye_width 0x34 (305 PS) (81% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 20 eye_width 0x34 (305 PS) (81% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 21 eye_width 0x34 (305 PS) (81% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 22 eye_width 0x32 (293 PS) (78% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 23 eye_width 0x31 (287 PS) (76% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 24 eye_width 0x2f (275 PS) (73% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 25 eye_width 0x2e (269 PS) (71% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 26 eye_width 0x2d (264 PS) (70% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 27 eye_width 0x2c (258 PS) (68% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 28 eye_width 0x2b (252 PS) (67% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 29 eye_width 0x29 (240 PS) (64% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 30 eye_width 0x29 (240 PS) (64% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 31 eye_width 0x29 (240 PS) (64% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 32 eye_width 0x27 (228 PS) (60% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 33 eye_width 0x27 (228 PS) (60% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 35 eye_width 0x24 (211 PS) (56% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 36 eye_width 0x23 (205 PS) (54% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 37 eye_width 0x21 (193 PS) (51% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 38 eye_width 0x20 (187 PS) (49% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 39 eye_width 0x20 (187 PS) (49% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 40 eye_width 0x1f (181 PS) (48% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 41 eye_width 0x1c (164 PS) (43% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 42 eye_width 0x1a (152 PS) (40% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 43 eye_width 0x18 (140 PS) (37% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 44 eye_width 0x14 (117 PS) (31% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 45 eye_width 0x10 (93 PS) (24% UI) N:1 C:2 ( DIMM_K0 ): WL: check if write vREF 17 is optimized choice N:1 C:2 ( DIMM_K0 ): WL: eye-- 0 eye- 79 eye 81 eye+ 79 eye++ 81 N:1 C:2 ( DIMM_K0 ): WL: final write vREF 17 N:1 C:2 ( DIMM_K0 ): Final WL: 1: dram_vref_dq 17 eye_width 0x34 (305 ps) (81% UI) N:1 C:2 ( DIMM_K0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 31 (181 PS) (48% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 36 (211 PS) (56% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 47 (275 PS) (73% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 48 (281 PS) (74% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 46 (269 PS) (71% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 44 (258 PS) (68% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 41 (240 PS) (64% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 39 (702 mv) group 0 [C1.W 32 (49% UI)] [C3.W 31 (48% UI)] common 32 (49% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 40 (720 mv) group 0 [C1.W 39 (60% UI)] [C3.W 36 (56% UI)] common 38 (59% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 41 (738 mv) group 0 [C1.W 46 (71% UI)] [C3.W 42 (65% UI)] common 44 (68% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 42 (756 mv) group 0 [C1.W 44 (68% UI)] [C3.W 47 (73% UI)] common 46 (71% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 43 (774 mv) group 0 [C1.W 41 (64% UI)] [C3.W 48 (74% UI)] common 45 (70% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 44 (792 mv) group 0 [C1.W 38 (59% UI)] [C3.W 46 (71% UI)] common 42 (65% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 45 (810 mv) group 0 [C1.W 33 (51% UI)] [C3.W 44 (68% UI)] common 39 (60% UI) N:1 C:3 - N:1 C:1 : RL COMMON VREF [42, 42, 42, 42] eye [46, 46, 46, 46] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:1 C:1 ( DIMM_J0 ): ::_4::dmc soft reset number 2 requested... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ DMCR PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 34 (199 PS) (53% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 43 (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 40 (234 PS) (62% UI) N:0 C:2 ( DIMM_C0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 39 (228 PS) (60% UI) Peak VREF [42, 42, 42, 42] eye [45, 45, 45, 45] N:0 C:2 ( DIMM_C0 ): Final RL: group 0 soc_vref 42 eye_width 44 68% N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 16 eye_width 0x37 (322 PS) (85% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 17 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 18 eye_width 0x34 (305 PS) (81% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 19 eye_width 0x35 (310 PS) (82% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 20 eye_width 0x37 (322 PS) (85% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 21 eye_width 0x34 (305 PS) (81% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 22 eye_width 0x34 (305 PS) (81% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 23 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 25 eye_width 0x31 (287 PS) (76% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 26 eye_width 0x2f (275 PS) (73% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 27 eye_width 0x2e (269 PS) (71% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 28 eye_width 0x2c (258 PS) (68% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 29 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 30 eye_width 0x2b (252 PS) (67% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 31 eye_width 0x2a (246 PS) (65% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 33 eye_width 0x26 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 35 eye_width 0x25 (217 PS) (57% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 36 eye_width 0x22 (199 PS) (53% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 37 eye_width 0x22 (199 PS) (53% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 38 eye_width 0x1e (176 PS) (46% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 39 eye_width 0x1d (170 PS) (45% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 40 eye_width 0x1a (152 PS) (40% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 41 eye_width 0x18 (140 PS) (37% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 42 eye_width 0x16 (129 PS) (34% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 43 eye_width 0x12 (105 PS) (28% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 44 eye_width 0x0e (82 PS) (21% UI) N:0 C:2 ( DIMM_C0 ): WL 1: dram_vref_dq 45 eye_width 0x09 (52 PS) (13% UI) N:0 C:2 ( DIMM_C0 ): WL: check if write vREF 16 is optimized choice N:0 C:2 ( DIMM_C0 ): WL: eye-- 751 eye- 0 eye 85 eye+ 82 eye++ 81 N:0 C:2 ( DIMM_C0 ): WL: final write vREF 16 N:0 C:2 ( DIMM_C0 ): Final WL: 1: dram_vref_dq 16 eye_width 0x38 (328 ps) (87% UI) N:0 C:2 ( DIMM_C0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 DMCL PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 31 (181 PS) (48% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 36 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 46 (269 PS) (71% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 48 (281 PS) (74% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 48 (281 PS) (74% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 45 (264 PS) (70% UI) N:0 C:3 ( DIMM_D0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 42 (246 PS) (65% UI) Peak VREF [43, 43, 43, 43] eye [48, 48, 48, 48] N:0 C:3 ( DIMM_D0 ): Final RL: group 0 soc_vref 43 eye_width 49 76% N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 16 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 17 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 18 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 19 eye_width 0x37 (322 PS) (85% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 20 eye_width 0x38 (328 PS) (87% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 21 eye_width 0x32 (293 PS) (78% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 22 eye_width 0x31 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 23 eye_width 0x32 (293 PS) (78% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 24 eye_width 0x31 (287 PS) (76% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 25 eye_width 0x30 (281 PS) (74% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 26 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 27 eye_width 0x2e (269 PS) (71% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 28 eye_width 0x2f (275 PS) (73% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 29 eye_width 0x2d (264 PS) (70% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 30 eye_width 0x2c (258 PS) (68% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 31 eye_width 0x2a (246 PS) (65% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 33 eye_width 0x27 (228 PS) (60% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 35 eye_width 0x24 (211 PS) (56% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 36 eye_width 0x22 (199 PS) (53% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 37 eye_width 0x22 (199 PS) (53% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 38 eye_width 0x21 (193 PS) (51% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 39 eye_width 0x1d (170 PS) (45% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 40 eye_width 0x1c (164 PS) (43% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 41 eye_width 0x1a (152 PS) (40% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 42 eye_width 0x18 (140 PS) (37% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 43 eye_width 0x15 (123 PS) (32% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 44 eye_width 0x13 (111 PS) (29% UI) N:0 C:3 ( DIMM_D0 ): WL 1: dram_vref_dq 45 eye_width 0x0f (88 PS) (23% UI) N:0 C:3 ( DIMM_D0 ): WL: check if write vREF 16 is optimized choice N:0 C:3 ( DIMM_D0 ): WL: eye-- 751 eye- 0 eye 87 eye+ 87 eye++ 87 N:0 C:3 ( DIMM_D0 ): WL: write vREF needed optimization to right 17 N:0 C:3 ( DIMM_D0 ): WL: final write vREF 17 N:0 C:3 ( DIMM_D0 ): Final WL: 1: dram_vref_dq 17 eye_width 0x38 (328 ps) (87% UI) N:0 C:3 ( DIMM_D0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 DMCL PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 40 (234 PS) (62% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 47 (846 mv) group 0 eye_width 44 (258 PS) (68% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 48 (864 mv) group 0 eye_width 42 (246 PS) (65% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 49 (882 mv) group 0 eye_width 40 (234 PS) (62% UI) N:1 C:1 ( DIMM_J0 ): RL 0: soc_vref_dq 50 (900 mv) group 0 eye_width 37 (217 PS) (57% UI) N:1 C:1 ( DIMM_J0 ): RL 1: soc_vref_dq 51 (918 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:1 ( DIMM_J0 ): Discontinuity in read leveling detected, restarting training DMCR PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 33 (193 PS) (51% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 38 (222 PS) (59% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 43 (252 PS) (67% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 47 (275 PS) (73% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 49 (287 PS) (76% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 48 (281 PS) (74% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 46 (269 PS) (71% UI) N:1 C:2 ( DIMM_K0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 43 (252 PS) (67% UI) Peak VREF [43, 43, 43, 43] eye [49, 49, 49, 49] N:1 C:2 ( DIMM_K0 ): Final RL: group 0 soc_vref 43 eye_width 49 76% N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 16 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 17 eye_width 0x34 (305 PS) (81% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 18 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 19 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 20 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 21 eye_width 0x33 (299 PS) (79% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 22 eye_width 0x31 (287 PS) (76% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 23 eye_width 0x30 (281 PS) (74% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 24 eye_width 0x30 (281 PS) (74% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 25 eye_width 0x2e (269 PS) (71% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 26 eye_width 0x2d (264 PS) (70% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 27 eye_width 0x2b (252 PS) (67% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 28 eye_width 0x2b (252 PS) (67% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 29 eye_width 0x2a (246 PS) (65% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 30 eye_width 0x29 (240 PS) (64% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 31 eye_width 0x29 (240 PS) (64% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 32 eye_width 0x29 (240 PS) (64% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 33 eye_width 0x27 (228 PS) (60% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 34 eye_width 0x26 (222 PS) (59% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 35 eye_width 0x25 (217 PS) (57% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 36 eye_width 0x23 (205 PS) (54% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 37 eye_width 0x21 (193 PS) (51% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 38 eye_width 0x20 (187 PS) (49% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 39 eye_width 0x20 (187 PS) (49% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 40 eye_width 0x1e (176 PS) (46% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 41 eye_width 0x1d (170 PS) (45% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 42 eye_width 0x19 (146 PS) (38% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 43 eye_width 0x16 (129 PS) (34% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 44 eye_width 0x14 (117 PS) (31% UI) N:1 C:2 ( DIMM_K0 ): WL 1: dram_vref_dq 45 eye_width 0x10 (93 PS) (24% UI) N:1 C:2 ( DIMM_K0 ): WL: check if write vREF 17 is optimized choice N:1 C:2 ( DIMM_K0 ): WL: eye-- 0 eye- 79 eye 81 eye+ 79 eye++ 79 N:1 C:2 ( DIMM_K0 ): WL: final write vREF 17 N:1 C:2 ( DIMM_K0 ): Final WL: 1: dram_vref_dq 17 eye_width 0x34 (305 ps) (81% UI) N:1 C:2 ( DIMM_K0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 32 (187 PS) (49% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 37 (217 PS) (57% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 42 (246 PS) (65% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 48 (281 PS) (74% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 48 (281 PS) (74% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 47 (275 PS) (73% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 44 (258 PS) (68% UI) N:1 C:3 ( DIMM_L0 ): RL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 42 (246 PS) (65% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 39 (702 mv) group 0 [C1.W 32 (49% UI)] [C3.W 32 (49% UI)] common 32 (49% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 40 (720 mv) group 0 [C1.W 40 (62% UI)] [C3.W 37 (57% UI)] common 39 (60% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 41 (738 mv) group 0 [C1.W 44 (68% UI)] [C3.W 42 (65% UI)] common 43 (67% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 42 (756 mv) group 0 [C1.W 42 (65% UI)] [C3.W 48 (74% UI)] common 45 (70% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 43 (774 mv) group 0 [C1.W 40 (62% UI)] [C3.W 48 (74% UI)] common 44 (68% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 44 (792 mv) group 0 [C1.W 37 (57% UI)] [C3.W 47 (73% UI)] common 42 (65% UI) N:1 C:1 ( DIMM_J0 ): soc_vref_dq 45 (810 mv) group 0 [C1.W 32 (49% UI)] [C3.W 44 (68% UI)] common 38 (59% UI) N:1 C:3 - N:1 C:1 : RL COMMON VREF [42, 42, 42, 42] eye [45, 45, 45, 45] ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ >>>>>>>>> N:1 C:1 ::_4::Final Read Level Failure... >>>>>>>>> ~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~+~ N:1 C:1 ( ): Final RL: soc_vref 42 eye_width 9 (13% UI) N:1 C:3 ( DIMM_L0 ): Final RL: soc_vref 42 eye_width 48 (74% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 16 eye_width 0x36 (316 PS) (84% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 17 eye_width 0x37 (322 PS) (85% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 18 eye_width 0x37 (322 PS) (85% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 19 eye_width 0x37 (322 PS) (85% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 20 eye_width 0x37 (322 PS) (85% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 21 eye_width 0x35 (310 PS) (82% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 22 eye_width 0x34 (305 PS) (81% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 23 eye_width 0x34 (305 PS) (81% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 24 eye_width 0x33 (299 PS) (79% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 25 eye_width 0x30 (281 PS) (74% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 26 eye_width 0x30 (281 PS) (74% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 27 eye_width 0x2e (269 PS) (71% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 28 eye_width 0x2d (264 PS) (70% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 29 eye_width 0x2c (258 PS) (68% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 30 eye_width 0x2b (252 PS) (67% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 31 eye_width 0x2b (252 PS) (67% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 32 eye_width 0x2a (246 PS) (65% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 33 eye_width 0x28 (234 PS) (62% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 34 eye_width 0x27 (228 PS) (60% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 35 eye_width 0x27 (228 PS) (60% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 36 eye_width 0x24 (211 PS) (56% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 37 eye_width 0x24 (211 PS) (56% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 38 eye_width 0x22 (199 PS) (53% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 39 eye_width 0x20 (187 PS) (49% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 40 eye_width 0x1e (176 PS) (46% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 41 eye_width 0x1c (164 PS) (43% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 42 eye_width 0x1a (152 PS) (40% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 43 eye_width 0x18 (140 PS) (37% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 44 eye_width 0x14 (117 PS) (31% UI) N:1 C:3 ( DIMM_L0 ): WL 1: dram_vref_dq 45 eye_width 0x0e (82 PS) (21% UI) N:1 C:3 ( DIMM_L0 ): WL: check if write vREF 17 is optimized choice N:1 C:3 ( DIMM_L0 ): WL: eye-- 0 eye- 84 eye 85 eye+ 85 eye++ 85 N:1 C:3 ( DIMM_L0 ): WL: final write vREF 17 N:1 C:3 ( DIMM_L0 ): Final WL: 1: dram_vref_dq 17 eye_width 0x37 (322 ps) (85% UI) N:1 C:3 ( DIMM_L0 ): cfactor: 1 dfactor: 3 RDRD DF RANK: 0x00000002 RDWR SM RANK: 0x00000004 RDWR DF RANK: 0x00000005 WRRD DF RANK: 0x00000002 WRWR DF RANK: 0x00000002 WRRD SM RANK: 0x00000002 Starting extended read leveling N:0 C:2 ( DIMM_C0 ): Starting extended read leveling N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 23 (134 PS) (35% UI) DLL:28-51 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 39 (702 mv) group 1 eye_width 28 (164 PS) (43% UI) DLL:22-50 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 39 (702 mv) group 2 eye_width 26 (152 PS) (40% UI) DLL:25-51 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 39 (702 mv) group 3 eye_width 25 (146 PS) (38% UI) DLL:26-51 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 28 (164 PS) (43% UI) DLL:23-51 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 40 (720 mv) group 1 eye_width 32 (187 PS) (49% UI) DLL:20-52 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 40 (720 mv) group 2 eye_width 31 (181 PS) (48% UI) DLL:23-54 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 40 (720 mv) group 3 eye_width 30 (176 PS) (46% UI) DLL:23-53 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 34 (199 PS) (53% UI) DLL:20-54 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 41 (738 mv) group 1 eye_width 36 (211 PS) (56% UI) DLL:17-53 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 41 (738 mv) group 2 eye_width 37 (217 PS) (57% UI) DLL:20-57 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 41 (738 mv) group 3 eye_width 36 (211 PS) (56% UI) DLL:20-56 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 37 (217 PS) (57% UI) DLL:17-54 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 42 (756 mv) group 1 eye_width 37 (217 PS) (57% UI) DLL:18-55 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 42 (756 mv) group 2 eye_width 42 (246 PS) (65% UI) DLL:16-58 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 42 (756 mv) group 3 eye_width 40 (234 PS) (62% UI) DLL:17-57 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 37 (217 PS) (57% UI) DLL:18-55 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 43 (774 mv) group 1 eye_width 39 (228 PS) (60% UI) DLL:17-56 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 43 (774 mv) group 2 eye_width 40 (234 PS) (62% UI) DLL:19-59 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 43 (774 mv) group 3 eye_width 39 (228 PS) (60% UI) DLL:18-57 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 35 (205 PS) (54% UI) DLL:20-55 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 44 (792 mv) group 1 eye_width 37 (217 PS) (57% UI) DLL:19-56 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 44 (792 mv) group 2 eye_width 38 (222 PS) (59% UI) DLL:21-59 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 44 (792 mv) group 3 eye_width 37 (217 PS) (57% UI) DLL:20-57 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 32 (187 PS) (49% UI) DLL:22-54 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 45 (810 mv) group 1 eye_width 36 (211 PS) (56% UI) DLL:17-53 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 45 (810 mv) group 2 eye_width 36 (211 PS) (56% UI) DLL:23-59 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 45 (810 mv) group 3 eye_width 35 (205 PS) (54% UI) DLL:22-57 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 29 (170 PS) (45% UI) DLL:25-54 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 46 (828 mv) group 1 eye_width 33 (193 PS) (51% UI) DLL:25-58 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 46 (828 mv) group 2 eye_width 32 (187 PS) (49% UI) DLL:25-57 N:0 C:2 ( DIMM_C0 ): ERL 1: soc_vref_dq 46 (828 mv) group 3 eye_width 32 (187 PS) (49% UI) DLL:25-57 N:0 C:3 ( DIMM_D0 ): Starting extended read leveling N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 24 (140 PS) (37% UI) DLL:28-52 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 39 (702 mv) group 1 eye_width 30 (176 PS) (46% UI) DLL:24-54 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 39 (702 mv) group 2 eye_width 22 (129 PS) (34% UI) DLL:27-49 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 39 (702 mv) group 3 eye_width 24 (140 PS) (37% UI) DLL:28-52 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 30 (176 PS) (46% UI) DLL:25-55 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 40 (720 mv) group 1 eye_width 35 (205 PS) (54% UI) DLL:21-56 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 40 (720 mv) group 2 eye_width 26 (152 PS) (40% UI) DLL:25-51 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 40 (720 mv) group 3 eye_width 29 (170 PS) (45% UI) DLL:25-54 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 35 (205 PS) (54% UI) DLL:22-57 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 41 (738 mv) group 1 eye_width 40 (234 PS) (62% UI) DLL:18-58 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 41 (738 mv) group 2 eye_width 32 (187 PS) (49% UI) DLL:22-54 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 41 (738 mv) group 3 eye_width 35 (205 PS) (54% UI) DLL:22-57 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 38 (222 PS) (59% UI) DLL:20-58 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 42 (756 mv) group 1 eye_width 42 (246 PS) (65% UI) DLL:16-58 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 42 (756 mv) group 2 eye_width 36 (211 PS) (56% UI) DLL:20-56 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 42 (756 mv) group 3 eye_width 39 (228 PS) (60% UI) DLL:20-59 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 37 (217 PS) (57% UI) DLL:16-53 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 43 (774 mv) group 1 eye_width 43 (252 PS) (67% UI) DLL:16-59 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 43 (774 mv) group 2 eye_width 39 (228 PS) (60% UI) DLL:17-56 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 43 (774 mv) group 3 eye_width 42 (246 PS) (65% UI) DLL:17-59 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 36 (211 PS) (56% UI) DLL:18-54 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 44 (792 mv) group 1 eye_width 42 (246 PS) (65% UI) DLL:15-57 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 44 (792 mv) group 2 eye_width 39 (228 PS) (60% UI) DLL:17-56 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 44 (792 mv) group 3 eye_width 39 (228 PS) (60% UI) DLL:20-59 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 34 (199 PS) (53% UI) DLL:20-54 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 45 (810 mv) group 1 eye_width 38 (222 PS) (59% UI) DLL:21-59 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 45 (810 mv) group 2 eye_width 35 (205 PS) (54% UI) DLL:22-57 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 45 (810 mv) group 3 eye_width 36 (211 PS) (56% UI) DLL:22-58 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 28 (164 PS) (43% UI) DLL:22-50 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 46 (828 mv) group 1 eye_width 36 (211 PS) (56% UI) DLL:21-57 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 46 (828 mv) group 2 eye_width 31 (181 PS) (48% UI) DLL:23-54 N:0 C:3 ( DIMM_D0 ): ERL 1: soc_vref_dq 46 (828 mv) group 3 eye_width 32 (187 PS) (49% UI) DLL:24-56 ERL:Peak VREF [42, 43, 42, 42] eye [37, 39, 42, 40] N:0 C:2 ( DIMM_C0 ): Info Address Mode : 2T (Addr Delay:1 CS Delay:0) Additional RL Delay : 6 cycle(s) Single-Rank load DLL: 0x30/0x80 cycle Multi-Rank load DLL: 0x20/0x80 cycle Wr DQS pre-launch : 0 cycle(s) Lanes 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TX_PS: 21 24 24 26 23 27 23 28 24 21 20 21 23 22 21 20 18 21 R_0 TX_CDLY: 2 2 2 1 0 1 1 1 0 2 2 2 1 0 1 1 1 0 R_0 TX_FDLY: 32 17 1 38 63 19 38 61 63 31 21 1 40 63 23 38 61 63 R_0 RX_PS: 39 36 35 33 36 36 38 39 37 37 36 39 37 39 38 40 37 36 R_0 RX_CDLY: 4 3 3 2 2 3 3 4 2 4 4 3 2 2 3 3 4 2 R_0 RX_FDLY: 24 58 17 58 24 4 40 1 14 28 0 20 54 17 7 43 6 12 N:0 C:2 ( DIMM_C0 ): Final ERL: group 0 soc_vref 42 eye_width 38 59% DLL:18-56 N:0 C:2 ( DIMM_C0 ): Final ERL: group 1 soc_vref 43 eye_width 39 60% DLL:14-53 N:0 C:2 ( DIMM_C0 ): Final ERL: group 2 soc_vref 42 eye_width 41 64% DLL:16-57 N:0 C:2 ( DIMM_C0 ): Final ERL: group 3 soc_vref 42 eye_width 39 60% DLL:18-57 ERL:Peak VREF [42, 43, 43, 43] eye [38, 43, 39, 42] N:0 C:3 ( DIMM_D0 ): Info Address Mode : 2T (Addr Delay:1 CS Delay:0) Additional RL Delay : 6 cycle(s) Single-Rank load DLL: 0x30/0x80 cycle Multi-Rank load DLL: 0x20/0x80 cycle Wr DQS pre-launch : 0 cycle(s) Lanes 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TX_PS: 23 22 24 26 22 24 23 25 23 20 18 22 23 22 21 19 20 17 R_0 TX_CDLY: 2 2 1 1 0 1 1 2 0 2 2 1 1 0 1 1 2 0 R_0 TX_FDLY: 32 12 57 36 63 23 34 0 63 32 15 61 39 63 27 40 7 63 R_0 RX_PS: 39 37 33 35 39 36 37 38 37 38 38 37 38 36 38 37 40 38 R_0 RX_CDLY: 4 3 3 2 2 2 3 4 2 4 3 3 2 2 3 3 4 2 R_0 RX_FDLY: 23 57 11 54 18 59 45 0 7 29 54 22 59 10 11 46 0 8 N:0 C:3 ( DIMM_D0 ): Final ERL: group 0 soc_vref 42 eye_width 37 57% DLL:15-52 N:0 C:3 ( DIMM_D0 ): Final ERL: group 1 soc_vref 43 eye_width 42 65% DLL:17-59 N:0 C:3 ( DIMM_D0 ): Final ERL: group 2 soc_vref 43 eye_width 39 60% DLL:17-56 N:0 C:3 ( DIMM_D0 ): Final ERL: group 3 soc_vref 43 eye_width 41 64% DLL:17-58 N:1 C:2 ( DIMM_K0 ): Starting extended read leveling N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 25 (146 PS) (38% UI) DLL:26-51 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 39 (702 mv) group 1 eye_width 30 (176 PS) (46% UI) DLL:23-53 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 39 (702 mv) group 2 eye_width 23 (134 PS) (35% UI) DLL:26-49 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 39 (702 mv) group 3 eye_width 21 (123 PS) (32% UI) DLL:29-50 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 30 (176 PS) (46% UI) DLL:21-51 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 40 (720 mv) group 1 eye_width 34 (199 PS) (53% UI) DLL:20-54 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 40 (720 mv) group 2 eye_width 28 (164 PS) (43% UI) DLL:24-52 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 40 (720 mv) group 3 eye_width 26 (152 PS) (40% UI) DLL:26-52 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 35 (205 PS) (54% UI) DLL:19-54 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 41 (738 mv) group 1 eye_width 38 (222 PS) (59% UI) DLL:18-56 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 41 (738 mv) group 2 eye_width 35 (205 PS) (54% UI) DLL:20-55 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 41 (738 mv) group 3 eye_width 32 (187 PS) (49% UI) DLL:23-55 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 39 (228 PS) (60% UI) DLL:16-55 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 42 (756 mv) group 1 eye_width 41 (240 PS) (64% UI) DLL:14-55 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 42 (756 mv) group 2 eye_width 38 (222 PS) (59% UI) DLL:19-57 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 42 (756 mv) group 3 eye_width 38 (222 PS) (59% UI) DLL:20-58 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 41 (240 PS) (64% UI) DLL:16-57 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 43 (774 mv) group 1 eye_width 42 (246 PS) (65% UI) DLL:14-56 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 43 (774 mv) group 2 eye_width 42 (246 PS) (65% UI) DLL:14-56 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 43 (774 mv) group 3 eye_width 41 (240 PS) (64% UI) DLL:19-60 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 38 (222 PS) (59% UI) DLL:16-54 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 44 (792 mv) group 1 eye_width 39 (228 PS) (60% UI) DLL:20-59 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 44 (792 mv) group 2 eye_width 41 (240 PS) (64% UI) DLL:14-55 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 44 (792 mv) group 3 eye_width 41 (240 PS) (64% UI) DLL:19-60 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 36 (211 PS) (56% UI) DLL:19-55 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 45 (810 mv) group 1 eye_width 35 (205 PS) (54% UI) DLL:22-57 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 45 (810 mv) group 2 eye_width 40 (234 PS) (62% UI) DLL:16-56 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 45 (810 mv) group 3 eye_width 40 (234 PS) (62% UI) DLL:20-60 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 30 (176 PS) (46% UI) DLL:22-52 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 46 (828 mv) group 1 eye_width 31 (181 PS) (48% UI) DLL:24-55 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 46 (828 mv) group 2 eye_width 38 (222 PS) (59% UI) DLL:18-56 N:1 C:2 ( DIMM_K0 ): ERL 1: soc_vref_dq 46 (828 mv) group 3 eye_width 37 (217 PS) (57% UI) DLL:23-60 N:1 C:3 ( DIMM_L0 ): Starting extended read leveling N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 39 (702 mv) group 0 eye_width 22 (129 PS) (34% UI) DLL:29-51 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 39 (702 mv) group 1 eye_width 29 (170 PS) (45% UI) DLL:23-52 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 39 (702 mv) group 2 eye_width 29 (170 PS) (45% UI) DLL:22-51 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 39 (702 mv) group 3 eye_width 24 (140 PS) (37% UI) DLL:26-50 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 40 (720 mv) group 0 eye_width 27 (158 PS) (42% UI) DLL:27-54 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 40 (720 mv) group 1 eye_width 33 (193 PS) (51% UI) DLL:21-54 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 40 (720 mv) group 2 eye_width 33 (193 PS) (51% UI) DLL:23-56 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 40 (720 mv) group 3 eye_width 30 (176 PS) (46% UI) DLL:23-53 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 41 (738 mv) group 0 eye_width 34 (199 PS) (53% UI) DLL:20-54 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 41 (738 mv) group 1 eye_width 36 (211 PS) (56% UI) DLL:19-55 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 41 (738 mv) group 2 eye_width 37 (217 PS) (57% UI) DLL:21-58 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 41 (738 mv) group 3 eye_width 35 (205 PS) (54% UI) DLL:20-55 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 42 (756 mv) group 0 eye_width 37 (217 PS) (57% UI) DLL:21-58 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 42 (756 mv) group 1 eye_width 40 (234 PS) (62% UI) DLL:16-56 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 42 (756 mv) group 2 eye_width 41 (240 PS) (64% UI) DLL:19-60 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 42 (756 mv) group 3 eye_width 39 (228 PS) (60% UI) DLL:18-57 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 43 (774 mv) group 0 eye_width 40 (234 PS) (62% UI) DLL:18-58 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 43 (774 mv) group 1 eye_width 39 (228 PS) (60% UI) DLL:18-57 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 43 (774 mv) group 2 eye_width 40 (234 PS) (62% UI) DLL:17-57 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 43 (774 mv) group 3 eye_width 40 (234 PS) (62% UI) DLL:18-58 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 44 (792 mv) group 0 eye_width 39 (228 PS) (60% UI) DLL:20-59 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 44 (792 mv) group 1 eye_width 36 (211 PS) (56% UI) DLL:20-56 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 44 (792 mv) group 2 eye_width 36 (211 PS) (56% UI) DLL:22-58 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 44 (792 mv) group 3 eye_width 38 (222 PS) (59% UI) DLL:19-57 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 45 (810 mv) group 0 eye_width 36 (211 PS) (56% UI) DLL:23-59 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 45 (810 mv) group 1 eye_width 34 (199 PS) (53% UI) DLL:23-57 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 45 (810 mv) group 2 eye_width 32 (187 PS) (49% UI) DLL:24-56 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 45 (810 mv) group 3 eye_width 35 (205 PS) (54% UI) DLL:22-57 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 46 (828 mv) group 0 eye_width 33 (193 PS) (51% UI) DLL:25-58 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 46 (828 mv) group 1 eye_width 31 (181 PS) (48% UI) DLL:25-56 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 46 (828 mv) group 2 eye_width 27 (158 PS) (42% UI) DLL:26-53 N:1 C:3 ( DIMM_L0 ): ERL 1: soc_vref_dq 46 (828 mv) group 3 eye_width 32 (187 PS) (49% UI) DLL:25-57 ERL:Peak VREF [43, 43, 43, 43] eye [41, 42, 42, 41] N:1 C:2 ( DIMM_K0 ): Info Address Mode : 2T (Addr Delay:1 CS Delay:0) Additional RL Delay : 6 cycle(s) Single-Rank load DLL: 0x30/0x80 cycle Multi-Rank load DLL: 0x20/0x80 cycle Wr DQS pre-launch : 0 cycle(s) Lanes 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TX_PS: 25 25 26 26 28 27 25 24 27 20 20 22 27 23 24 20 25 22 R_0 TX_CDLY: 2 2 1 1 0 1 1 1 0 2 2 1 1 0 1 1 1 0 R_0 TX_FDLY: 20 4 46 31 63 17 32 54 60 21 9 54 31 63 21 32 58 63 R_0 RX_PS: 39 36 34 35 35 35 39 36 39 37 36 38 36 38 37 39 39 39 R_0 RX_CDLY: 4 3 3 2 2 2 3 4 2 4 3 3 2 2 2 3 4 2 R_0 RX_FDLY: 14 41 9 47 7 55 43 0 1 7 48 10 50 15 53 45 0 4 N:1 C:2 ( DIMM_K0 ): Final ERL: group 0 soc_vref 43 eye_width 41 64% DLL:14-55 N:1 C:2 ( DIMM_K0 ): Final ERL: group 1 soc_vref 43 eye_width 40 62% DLL:16-56 N:1 C:2 ( DIMM_K0 ): Final ERL: group 2 soc_vref 43 eye_width 42 65% DLL:14-56 N:1 C:2 ( DIMM_K0 ): Final ERL: group 3 soc_vref 43 eye_width 41 64% DLL:19-60 ERL:Peak VREF [43, 42, 42, 43] eye [40, 40, 41, 40] N:1 C:3 ( DIMM_L0 ): Info Address Mode : 2T (Addr Delay:1 CS Delay:0) Additional RL Delay : 6 cycle(s) Single-Rank load DLL: 0x30/0x80 cycle Multi-Rank load DLL: 0x20/0x80 cycle Wr DQS pre-launch : 0 cycle(s) Lanes 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TX_PS: 24 25 21 26 25 23 28 23 28 18 20 21 22 23 21 23 23 22 R_0 TX_CDLY: 2 2 2 1 0 1 1 2 1 2 2 2 1 0 1 1 2 1 R_0 TX_FDLY: 37 17 3 42 63 27 39 6 0 40 20 3 46 63 32 41 6 2 R_0 RX_PS: 38 38 38 39 37 38 39 37 37 37 39 37 36 36 40 37 41 38 R_0 RX_CDLY: 4 3 3 2 2 3 3 4 2 4 3 3 2 2 2 3 4 2 R_0 RX_FDLY: 32 60 22 55 21 0 47 2 16 32 62 31 63 14 60 47 0 18 N:1 C:3 ( DIMM_L0 ): Final ERL: group 0 soc_vref 43 eye_width 40 62% DLL:19-59 N:1 C:3 ( DIMM_L0 ): Final ERL: group 1 soc_vref 42 eye_width 40 62% DLL:17-57 N:1 C:3 ( DIMM_L0 ): Final ERL: group 2 soc_vref 42 eye_width 42 65% DLL:16-58 N:1 C:3 ( DIMM_L0 ): Final ERL: group 3 soc_vref 43 eye_width 39 60% DLL:18-57 Save VREF values to flash snor_erase: off=0x3ff0000, len=0x10000 ----------------------------------- ENV Variable Settings ----------------------------------- Name : Value ----------------------------------- turbo : 2 smt : 4 corefreq : 2199 numcores : 32 icispeed : 1 socnclk : 666 socsclk : 1199 memclk : 2199 ddrspeed_auto : 1 ddrspeed : 2400 progcpufreq : 1 progdevfreq : 1 dmc_node_channel_mask : 0000ffff thermcontrol : 1 thermlimit : 110 enter_debug_shell : 0 dbg_speed_up_ddr_lvl : 0 enable_dram_scrub : 0 ipmbcontrol : 1 ddr_dmt_advanced : 0 cppccontrol : 1 loglevel : 0 uart_params : 115200/8-N-1 none core_feature_mask : 0 sys_feature_mask : 0x00000000 ddr_refresh_rate : 1 fw_feature_mask : 0x00000000 dram_ce_threshold : 1 dram_ce_step_threshold: 0 dram_ce_record_max : 10 dram_ce_window : 60 sec dram_ce_leak_rate : 2000 msec/error pcie_ce_threshold : 1 pcie_ce_window : 30 sec pcie_ce_leak_rate : 15000 msec/error ----------------------------------- CHAN 2 total delay: 1957 CHAN 3 total delay: 1556 CHAN 2 total delay: 2283 CHAN 3 total delay: 1560 TGE Clear Memory (N:0 C:2): -- PASS TGE Clear Memory (N:0 C:3): -- PASS TGE Clear Memory (N:1 C:2): -- PASS TGE Clear Memory (N:1 C:3): -- PASS Enabled DIMM Channels: N:0 C:2 N:0 C:3 N:1 C:2 N:1 C:3 fdt_prop_set_int: Failed to set SOCKET_ID2/AVAIL_DIMMS_MASK=0xffff0000 in FDT fdt_prop_set_int: Failed to set SOCKET_ID3/AVAIL_DIMMS_MASK=0xffff0000 in FDT BAR0 Base 00004000 Limit 00007FF3 chan_xlation 00004008 node_xlation 00000000 BAR1 Base 00080001 Limit 000FEFF3 chan_xlation 0007C008 node_xlation 00000000 BAR2 Base 00880001 Limit 00FFCFF3 chan_xlation 007FD008 node_xlation 00000000 BAR3 Base 00FFD001 Limit 00FFFFF3 chan_xlation 00FFD008 node_xlation 00000002 BAR4 Base 08800001 Limit 08FFCFF3 chan_xlation 087FD008 node_xlation 00000002 BAR0 Base 00004000 Limit 00007FF3 chan_xlation 00004008 node_xlation 00000000 BAR1 Base 00080001 Limit 000FEFF3 chan_xlation 0007C008 node_xlation 00000000 BAR2 Base 00880001 Limit 00FFCFF3 chan_xlation 007FD008 node_xlation 00000000 BAR3 Base 00FFD001 Limit 00FFFFF3 chan_xlation 00FFD008 node_xlation 00000002 BAR4 Base 08800001 Limit 08FFCFF3 chan_xlation 087FD008 node_xlation 00000002 Node 0 mem descriptor list: 2 entries Base 0x00000000_80000000 size 0x00000000_7F000000 S_NS 0 Base 0x00000008_80000000 size 0x00000007_7D000000 S_NS 0 Node 1 mem descriptor list: 2 entries Base 0x0000000F_FD000000 size 0x00000000_03000000 S_NS 0 Base 0x00000088_00000000 size 0x00000007_FD000000 S_NS 0 Node0: SKU: CN9980-2200BG4077-Y22-G Serial: 000020D9-20EB3296 Node1: SKU: CN9980-2200BG4077-Y22-G Serial: 000020D9-28EB320A Press 's' to enter shell. Starting autoboot in : 0 Node 0 mem descriptor list: 2 entries Base 0x00000000_80000000 size 0x00000000_7F000000 S_NS 0 Base 0x00000008_80000000 size 0x00000007_7D000000 S_NS 0 Node 1 mem descriptor list: 2 entries Base 0x0000000F_FD000000 size 0x00000000_03000000 S_NS 0 Base 0x00000088_00000000 size 0x00000007_FD000000 S_NS 0 == Setup Boot2 and Execute: Secure Boot disabled M3 RAM already loaded. Bypass M3 RAM already loaded. Bypass Measuring M3 0x20c3010-0x20cb9a4 to PCR0 Loaded image type 3, offset 70000, size 8e15 CRC Calculated 8cb62b4c Loaded image type 4, offset 60000, size 92d8 CRC Calculated f50d468c Measuring FIP 0x84000000-0x850b0000 to PCR0 Loaded image type 5, offset 80000, size 10b0000 Measuring BOOT1 ENV 0x23ea3e8-0x23ea4ac to PCR1 boot1 image hash: e0d98b222c779a7260b8f9fe79c313de66267b11e947d535ef1155f575fdde34 FIP image hash: 6f9a0e9c1fa8c066aa5672703071080163b7b46d7a443605189a21a9ee52cc24 M3 image hash: 7e5781baf4539628138da39a0cac4bf39cf670e607814574e5b3b7f62b2f649f FDT image hash: 4a6f420407714f2a3958eb37dde9ad6c56b890c1dd6f1f371372472375c9ff6d BOOT1 ENV image hash: 8f1bccf42718c7e8936d448e8d9f749889eecf0dc3a9dddb516a554b63156a7a Initialized CPLD access on chipselect : 2 Executing Boot2 at 4000000 === Boot1 Jump to trusted FW initialization ============================== Booting Trusted Firmware TX2-FW-Release-7.3-build_01 Built : 16:20:21, Aug 13 2020 ============================== NOTICE: BL2: TX2-FW-Release-7.3-build_01 NOTICE: BL2: Built : 16:20:21, Aug 13 2020 INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 INFO: Loading image id=3 at address 0x6dde000 INFO: Image id=3 loaded: 0x6dde000 - 0x6e02b28 INFO: BL2: Loading image id 4 INFO: Loading image id=4 at address 0x4dde000 INFO: Image id=4 loaded: 0x4dde000 - 0x505e000 INFO: BL2: Loading image id 5 INFO: Loading image id=5 at address 0xc0000000 INFO: Image id=5 loaded: 0xc0000000 - 0xc0df0000 NOTICE: BL2: Booting BL31 INFO: Entry point address = 0x6dde000 INFO: SPSR = 0x3cd ============================== Booting Trusted Firmware TX2-FW-Release-7.3-build_01 Built : 16:20:26, Aug 13 2020 ============================== INFO: Core feature mask set to 0 INFO: FW feature mask set to 0 INFO: Node 0: 2 memory descriptors INFO: Base: 0x80000000 Size: 0x7f000000 INFO: Base: 0x880000000 Size: 0x77d000000 INFO: Node 1: 2 memory descriptors INFO: Base: 0xffd000000 Size: 0x3000000 INFO: Base: 0x8800000000 Size: 0x7fd000000 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N0:C0:D1 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N0:C1:D1 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N0:C2:D1 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N0:C3:D1 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N0:C4:D0 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N0:C5:D0 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N0:C6:D0 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N0:C7:D0 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N1:C0:D1 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N1:C1:D1 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N1:C2:D1 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N1:C3:D1 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N1:C4:D0 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N1:C5:D0 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N1:C6:D0 fdt_get_int: Property SPD_SIZE not found. NOTICE: DIMM not installed for N1:C7:D0 INFO: Node0: M3_HEARTBEAT_GPIO not found INFO: DIMM_E1 not found in DIMMS node: INFO: DIMM_F1 not found in DIMMS node: INFO: DIMM_G1 not found in DIMMS node: INFO: DIMM_H1 not found in DIMMS node: INFO: Node1: M3_HEARTBEAT_GPIO not found INFO: DIMM_E1 not found in DIMMS node: INFO: DIMM_F1 not found in DIMMS node: INFO: DIMM_G1 not found in DIMMS node: INFO: DIMM_H1 not found in DIMMS node: INFO: M3:0: Sending M3 status request NOTICE: M3:0: Ready received. INFO: M3:1: Sending M3 status request NOTICE: M3:1: Ready received. INFO: M3:0: Sending core freq update INFO: M3:1: Sending core freq update INFO: M3:0: Sending dev freq update INFO: M3:0: Sending SOCS freq update INFO: M3:0: Sending MEM freq update INFO: M3:1: Sending dev freq update INFO: M3:1: Sending SOCS freq update INFO: M3:1: Sending MEM freq update INFO: GICv3 without legacy support detected. ARM GICV3 driver initialized in EL3 SHUTDOWN_REQ_GPIO found: 63 SMBALERT_GPIO not found SMBALERT_GPIO not found Disabling ICI intf.; Enabling GPIO mode gpio_intr_cfg(node=0, gpio_num=63) GPIO status before : 0xfffffcff GPIO status after : 0x7ffffcff configured 63 TCA9555 specified scan_fdt_for_hotplug : i=0, pcihp_gpio_count=1 TCA9555 specified scan_fdt_for_hotplug : i=0, pcihp_gpio_count=1 TCA9555 specified scan_fdt_for_hotplug : i=0, pcihp_gpio_count=1 TCA9555 specified pcihp_gpio[0].enabled=1 pci0 register as TCA95555 with address as 0x20 ERROR: Fail TCA9555 access. PCI hotplug disabled. INFO: GPIO<31> configured for PCI hotplug. Disabling SPI intf.; Enabling GPIO mode gpio_intr_cfg(node=0, gpio_num=31) GPIO status before : 0xffdfef35 GPIO status after : 0x7fdfef35 configured 31 RAS_BMC_CE_GPIO not found RAS_BMC_UER_GPIO not found RAS_BMC_UEU_GPIO not found NOTICE: Node 0: 32 cores, 4 threads per core NOTICE: Node 1: 32 cores, 4 threads per core INFO: Secure SSIF init successful. INFO: RAS: M.2 topology was not found INFO: RAS: Drivers initialized WARNING: TIMER: timer with hd =0 already started! WARNING: TIMER: timer with hd =0 already started! NOTICE: RAS: DMC interrupt handler installed INFO: CRASHDUMP_M3_GPIO = -1 INFO: CRASHDUMP_M3_GPIO = -1 Disabling ICI intf.; Enabling GPIO mode GPIO status before : 0x00003fff GPIO status after : 0x00003ffb INFO: BL31: Initializing runtime services INFO: BL31: Initializing BL32 INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xc0000000 INFO: SPSR = 0x3c9 Checkpoint 2F Checkpoint 2C Checkpoint 31 Checkpoint 32 Checkpoint 4F Checkpoint 60 Checkpoint 61 Checkpoint 9A Checkpoint 78 BIOS Ver:F34 BmcFwVersion = 12.58.03 BMC IP : 192.168.0.69 Checkpoint 90 Checkpoint 91 Checkpoint 92 Checkpoint 94 Checkpoint 94 Checkpoint 95 Checkpoint 96 Checkpoint 92 Checkpoint 94 Checkpoint 94 Checkpoint 95 Checkpoint 97 Checkpoint 98 Checkpoint 9D Checkpoint 9C Checkpoint B4 Checkpoint B4 Checkpoint 9D Checkpoint 9C Checkpoint B4 Checkpoint B4 Checkpoint B4 Checkpoint B4 Checkpoint B4 Checkpoint B4 Checkpoint B4 Checkpoint 9D Checkpoint 9C Checkpoint 9D Checkpoint 9C Checkpoint 92 Checkpoint 96 Checkpoint 96 Checkpoint 96 Checkpoint A0 Checkpoint A2 Checkpoint 96 Checkpoint A0 Checkpoint A2 Checkpoint 92 Checkpoint A0 HDD Serial Number = PNY21012101040109608 HDD Serial Number = PNY21012101040109601 Checkpoint AD Checkpoint 78 Consoles: EFI console Reading loader env vars from /efi/freebsd/loader.env Setting currdev to disk9p1: FreeBSD/arm64 EFI loader, Revision 1.1 (Thu Feb 24 05:14:55 UTC 2022 root@releng1.nyi.freebsd.org) Command line arguments: loader.efi Image base: 0xf3549000 EFI version: 2.70 EFI Firmware: American Megatrends (rev 5.13) Console: efi (0x20000000) Load Path: \EFI\BOOT\BOOTAA64.EFI Load Device: PciRoot(0x1)/Pci(0x7,0x0)/Pci(0x0,0x0)/NVMe(0x1,FA-2C-B0-71-59-38-25-00)/HD(1,GPT,240C2F14-9782-11EC-9D4D-0C42A1E384A4,0x28,0x82000) BootCurrent: 000b BootOrder: 000b[*] 0001 0004 0005 0006 0007 0002 0008 0000 BootInfo Path: HD(1,GPT,240C2F14-9782-11EC-9D4D-0C42A1E384A4,0x28,0x82000)/\EFI\BOOT\BOOTAA64.EFI Ignoring Boot000b: Only one DP found Trying ESP: PciRoot(0x1)/Pci(0x7,0x0)/Pci(0x0,0x0)/NVMe(0x1,FA-2C-B0-71-59-38-25-00)/HD(1,GPT,240C2F14-9782-11EC-9D4D-0C42A1E384A4,0x28,0x82000) Setting currdev to disk9p1: Trying: PciRoot(0x1)/Pci(0x7,0x0)/Pci(0x0,0x0)/NVMe(0x1,FA-2C-B0-71-59-38-25-00)/HD(2,GPT,30DB4D76-9783-11EC-9D4D-0C42A1E384A4,0x82028,0x1B800000) Setting currdev to disk9p2: \ Loading /boot/defaults/loader.conf Loading /boot/defaults/loader.conf Loading /boot/device.hints Loading /boot/loader.conf Loading /boot/loader.conf.local ?c| / ______ ____ _____ _____ | ____| | _ \ / ____| __ \ | |___ _ __ ___ ___ | |_) | (___ | | | | | ___| '__/ _ \/ _ \| _ < \___ \| | | | | | | | | __/ __/| |_) |____) | |__| | | | | | | | || | | | |_| |_| \___|\___||____/|_____/|_____/ ``` ` s` `.....---.......--.``` -/ /---------- Welcome to FreeBSD -----------\ +o .--` /y:` +. | | yo`:. :o `+- | 1. Boot Multi user [Enter] | y/ -/` -o/ | 2. Boot Single user | .- ::/sy+:. | 3. Escape to loader prompt | / `-- / | 4. Reboot | `: :` | 5. Cons: Dual (Video primary) | `: :` | | / / | Options: | .- -. | 6. Kernel: default/kernel (1 of 2) | -- -. | 7. Boot Options | `:` `:` | | .-- `--. | | .---.....----. \-----------------------------------------/ Autoboot in 0 seconds. [Space] to pause Loading kernel... /boot/kernel/kernel text=0x2a8 text=0x8ce210 text=0x2773f4 data=0x1bff28 data=0x0+0x350000 0x8+0x140eb0+0x8+0x167c0f/ Loading configured modules... /boot/entropy size=0x1000 /etc/hostid size=0x25 No valid device tree blob found! WARNING! Trying to fire up the kernel, but no device tree blob found! EFI framebuffer information: addr, size 0x40000000, 0x12c000 dimensions 640 x 480 stride 640 masks 0x00ff0000, 0x0000ff00, 0x000000ff, 0xff000000 ---<>--- GDB: no debug ports present KDB: debugger backends: ddb KDB: current backend: ddb Copyright (c) 1992-2022 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 14.0-CURRENT #1 main-n255161-c4585b938a0: Wed May 4 03:49:18 EDT 2022 root@mars.morante.com:/usr/obj/usr/src/arm64.aarch64/sys/MARS arm64 FreeBSD clang version 13.0.0 (git@github.com:llvm/llvm-project.git llvmorg-13.0.0-0-gd7b669b3a303) WARNING: WITNESS option enabled, expect reduced performance. VT(efifb): resolution 640x480 module firmware already present! real memory = 68648960000 (65468 MB) avail memory = 66849816576 (63752 MB) Starting CPU 1 (100) Starting CPU 2 (200) Starting CPU 3 (300) Starting CPU 4 (400) Starting CPU 5 (500) Starting CPU 6 (600) Starting CPU 7 (700) Starting CPU 8 (800) Starting CPU 9 (900) Starting CPU 10 (a00) Starting CPU 11 (b00) Starting CPU 12 (c00) Starting CPU 13 (d00) Starting CPU 14 (e00) Starting CPU 15 (f00) Starting CPU 16 (1000) Starting CPU 17 (1100) Starting CPU 18 (1200) Starting CPU 19 (1300) Starting CPU 20 (1400) Starting CPU 21 (1500) Starting CPU 22 (1600) Starting CPU 23 (1700) Starting CPU 24 (1800) Starting CPU 25 (1900) Starting CPU 26 (1a00) Starting CPU 27 (1b00) Starting CPU 28 (1c00) Starting CPU 29 (1d00) Starting CPU 30 (1e00) Starting CPU 31 (1f00) INFO: Node: 0 :: REP: 0x0, REP-FAIL: 0x0, MBIST: 0x0, MBIST-FAIL: 0x823c3c Starting CPU 32 (1) Starting CPU 33 (101) Starting CPU 34 (201) Starting CPU 35 (301) Starting CPU 36 (401) Starting CPU 37 (501) Starting CPU 38 (601) Starting CPU 39 (701) Starting CPU 40 (801) Starting CPU 41 (901) Starting CPU 42 (a01) Starting CPU 43 (b01) Starting CPU 44 (c01) Starting CPU 45 (d01) Starting CPU 46 (e01) Starting CPU 47 (f01) Starting CPU 48 (1001) Starting CPU 49 (1101) Starting CPU 50 (1201) Starting CPU 51 (1301) Starting CPU 52 (1401) Starting CPU 53 (1501) Starting CPU 54 (1601) Starting CPU 55 (1701) Starting CPU 56 (1801) Starting CPU 57 (1901) Starting CPU 58 (1a01) Starting CPU 59 (1b01) Starting CPU 60 (1c01) Starting CPU 61 (1d01) Starting CPU 62 (1e01) Starting CPU 63 (1f01) Starting CPU 64 (2) Starting CPU 65 (102) Starting CPU 66 (202) Starting CPU 67 (302) Starting CPU 68 (402) Starting CPU 69 (502) Starting CPU 70 (602) Starting CPU 71 (702) Starting CPU 72 (802) Starting CPU 73 (902) Starting CPU 74 (a02) Starting CPU 75 (b02) Starting CPU 76 (c02) Starting CPU 77 (d02) Starting CPU 78 (e02) Starting CPU 79 (f02) Starting CPU 80 (1002) Starting CPU 81 (1102) Starting CPU 82 (1202) Starting CPU 83 (1302) Starting CPU 84 (1402) Starting CPU 85 (1502) Starting CPU 86 (1602) Starting CPU 87 (1702) Starting CPU 88 (1802) Starting CPU 89 (1902) Starting CPU 90 (1a02) Starting CPU 91 (1b02) Starting CPU 92 (1c02) Starting CPU 93 (1d02) Starting CPU 94 (1e02) Starting CPU 95 (1f02) Starting CPU 96 (3) Starting CPU 97 (103) Starting CPU 98 (203) Starting CPU 99 (303) Starting CPU 100 (403) Starting CPU 101 (503) Starting CPU 102 (603) Starting CPU 103 (703) Starting CPU 104 (803) Starting CPU 105 (903) Starting CPU 106 (a03) Starting CPU 107 (b03) Starting CPU 108 (c03) Starting CPU 109 (d03) Starting CPU 110 (e03) Starting CPU 111 (f03) Starting CPU 112 (1003) Starting CPU 113 (1103) Starting CPU 114 (1203) Starting CPU 115 (1303) Starting CPU 116 (1403) Starting CPU 117 (1503) Starting CPU 118 (1603) Starting CPU 119 (1703) Starting CPU 120 (1803) Starting CPU 121 (1903) Starting CPU 122 (1a03) Starting CPU 123 (1b03) Starting CPU 124 (1c03) Starting CPU 125 (1d03) Starting CPU 126 (1e03) Starting CPU 127 (1f03) Starting CPU 128 (10000) Starting CPU 129 (10100) Starting CPU 130 (10200) Starting CPU 131 (10300) Starting CPU 132 (10400) Starting CPU 133 (10500) Starting CPU 134 (10600) Starting CPU 135 (10700) Starting CPU 136 (10800) Starting CPU 137 (10900) Starting CPU 138 (10a00) Starting CPU 139 (10b00) Starting CPU 140 (10c00) Starting CPU 141 (10d00) Starting CPU 142 (10e00) Starting CPU 143 (10f00) Starting CPU 144 (11000) Starting CPU 145 (11100) Starting CPU 146 (11200) Starting CPU 147 (11300) Starting CPU 148 (11400) Starting CPU 149 (11500) Starting CPU 150 (11600) Starting CPU 151 (11700) Starting CPU 152 (11800) Starting CPU 153 (11900) Starting CPU 154 (11a00) Starting CPU 155 (11b00) Starting CPU 156 (11c00) Starting CPU 157 (11d00) Starting CPU 158 (11e00) Starting CPU 159 (11f00) INFO: Node: 1 :: REP: 0x0, REP-FAIL: 0x0, MBIST: 0x0, MBIST-FAIL: 0x823c3c Starting CPU 160 (10001) Starting CPU 161 (10101) Starting CPU 162 (10201) Starting CPU 163 (10301) Starting CPU 164 (10401) Starting CPU 165 (10501) Starting CPU 166 (10601) Starting CPU 167 (10701) Starting CPU 168 (10801) Starting CPU 169 (10901) Starting CPU 170 (10a01) Starting CPU 171 (10b01) Starting CPU 172 (10c01) Starting CPU 173 (10d01) Starting CPU 174 (10e01) Starting CPU 175 (10f01) Starting CPU 176 (11001) Starting CPU 177 (11101) Starting CPU 178 (11201) Starting CPU 179 (11301) Starting CPU 180 (11401) Starting CPU 181 (11501) Starting CPU 182 (11601) Starting CPU 183 (11701) Starting CPU 184 (11801) Starting CPU 185 (11901) Starting CPU 186 (11a01) Starting CPU 187 (11b01) Starting CPU 188 (11c01) Starting CPU 189 (11d01) Starting CPU 190 (11e01) Starting CPU 191 (11f01) Starting CPU 192 (10002) Starting CPU 193 (10102) Starting CPU 194 (10202) Starting CPU 195 (10302) Starting CPU 196 (10402) Starting CPU 197 (10502) Starting CPU 198 (10602) Starting CPU 199 (10702) Starting CPU 200 (10802) Starting CPU 201 (10902) Starting CPU 202 (10a02) Starting CPU 203 (10b02) Starting CPU 204 (10c02) Starting CPU 205 (10d02) Starting CPU 206 (10e02) Starting CPU 207 (10f02) Starting CPU 208 (11002) Starting CPU 209 (11102) Starting CPU 210 (11202) Starting CPU 211 (11302) Starting CPU 212 (11402) Starting CPU 213 (11502) Starting CPU 214 (11602) Starting CPU 215 (11702) Starting CPU 216 (11802) Starting CPU 217 (11902) Starting CPU 218 (11a02) Starting CPU 219 (11b02) Starting CPU 220 (11c02) Starting CPU 221 (11d02) Starting CPU 222 (11e02) Starting CPU 223 (11f02) Starting CPU 224 (10003) Starting CPU 225 (10103) Starting CPU 226 (10203) Starting CPU 227 (10303) Starting CPU 228 (10403) Starting CPU 229 (10503) Starting CPU 230 (10603) Starting CPU 231 (10703) Starting CPU 232 (10803) Starting CPU 233 (10903) Starting CPU 234 (10a03) Starting CPU 235 (10b03) Starting CPU 236 (10c03) Starting CPU 237 (10d03) Starting CPU 238 (10e03) Starting CPU 239 (10f03) Starting CPU 240 (11003) Starting CPU 241 (11103) Starting CPU 242 (11203) Starting CPU 243 (11303) Starting CPU 244 (11403) Starting CPU 245 (11503) Starting CPU 246 (11603) Starting CPU 247 (11703) Starting CPU 248 (11803) Starting CPU 249 (11903) Starting CPU 250 (11a03) Starting CPU 251 (11b03) Starting CPU 252 (11c03) Starting CPU 253 (11d03) Starting CPU 254 (11e03) Starting CPU 255 (11f03) FreeBSD/SMP: Multiprocessor System Detected: 256 CPUs random: unblocking device. random: entropy device external interface MAP 802f0000 mode 2 pages 16 MAP c0000000 mode 2 pages 3568 MAP fdc80000 mode 2 pages 2656 MAP fe810000 mode 2 pages 1184 MAP 402070000 mode 0 pages 1 MAP 402146000 mode 0 pages 1 MAP 402180000 mode 0 pages 16 MAP 4021a0000 mode 0 pages 16 kbd0 at kbdmux0 acpi0: acpi0: Power Button (fixed) acpi0: Sleep Button (fixed) acpi0: Could not update all GPEs: AE_NOT_CONFIGURED psci0: on acpi0 gic0: iomem 0x400080000-0x40009ffff,0x401000000-0x401ffffff,0x441000000-0x441ffffff on acpi0 its0: numa-domain 0 on gic0 its1: numa-domain 1 on gic0 generic_timer0: irq 10,11,12 on acpi0 Timecounter "ARM MPCore Timecounter" frequency 200000000 Hz quality 1000 Event timer "ARM MPCore Eventtimer" frequency 200000000 Hz quality 1000 efirtc0: efirtc0: registered as a time-of-day clock, resolution 1.000000s apei0: on acpi0 pmu0: on acpi0 acpi_button0: on acpi0 pcib0: numa-domain 0 on acpi0 pci0: numa-domain 0 on pcib0 pcib0: Failed to translate resource 4224100042230000-422410004223ffff type 3 for (null) pcib0: Failed to translate resource 0-ffffffffffffffff type 3 for (null) pcib0: Failed to translate resource 4224000042210000-422400004221ffff type 3 for (null) pcib0: Failed to translate resource 0-ffffffffffffffff type 3 for (null) pcib1: irq 269 at device 1.0 numa-domain 0 on pci0 pci1: numa-domain 0 on pcib1 pcib2: irq 270 at device 2.0 numa-domain 0 on pci0 pci2: numa-domain 0 on pcib2 pcib3: irq 271 at device 3.0 numa-domain 0 on pci0 pci3: numa-domain 0 on pcib3 pcib4: irq 272 at device 4.0 numa-domain 0 on pci0 pci4: numa-domain 0 on pcib4 pcib5: irq 273 at device 5.0 numa-domain 0 on pci0 pci5: numa-domain 0 on pcib5 pcib6: irq 274 at device 6.0 numa-domain 0 on pci0 pci6: numa-domain 0 on pcib6 pcib7: at device 7.0 numa-domain 0 on pci0 pci7: numa-domain 0 on pcib7 pci7: at device 0.0 (no driver attached) pci7: at device 0.1 (no driver attached) pcib8: irq 275 at device 8.0 numa-domain 0 on pci0 pci8: numa-domain 0 on pcib8 pcib9: irq 276 at device 9.0 numa-domain 0 on pci0 pci9: numa-domain 0 on pcib9 pcib10: irq 277 at device 10.0 numa-domain 0 on pci0 pci10: numa-domain 0 on pcib10 pcib11: at device 11.0 numa-domain 0 on pci0 pci11: numa-domain 0 on pcib11 pci11: at device 0.0 (no driver attached) pci11: at device 0.1 (no driver attached) pcib12: at device 12.0 numa-domain 0 on pci0 pci12: numa-domain 0 on pcib12 pcib13: at device 0.0 numa-domain 0 on pci12 pci13: numa-domain 0 on pcib13 vgapci0: mem 0x40000000-0x41ffffff,0x42000000-0x4201ffff at device 0.0 numa-domain 0 on pci13 pcib14: at device 13.0 numa-domain 0 on pci0 pci14: numa-domain 0 on pcib14 mpr0: mem 0x42140000-0x4214ffff,0x42100000-0x4213ffff at device 0.0 numa-domain 0 on pci14 mpr0: Firmware: 15.00.00.00, Driver: 23.00.00.00-fbsd mpr0: IOCCapabilities: 6985c pcib15: irq 278 at device 14.0 numa-domain 0 on pci0 pci15: numa-domain 0 on pcib15 xhci0: mem 0x10006130000-0x1000613ffff,0x10006120000-0x1000612ffff at device 15.0 numa-domain 0 on pci0 xhci0: 64 bytes context size, 64-bit DMA usbus0 numa-domain 0 on xhci0 xhci1: mem 0x10006110000-0x1000611ffff,0x10006100000-0x1000610ffff at device 15.1 numa-domain 0 on pci0 xhci1: 64 bytes context size, 64-bit DMA usbus1 numa-domain 0 on xhci1 ahci0: mem 0x42220000-0x4222ffff at device 16.0 numa-domain 0 on pci0 pcib0: Failed to translate resource 0-ffffffffffffffff type 3 for ahci0 ahci0: 0x10000 bytes of rid 0x18 res 3 failed (0, 0xffffffffffffffff). device_attach: ahci0 attach returned 6 ahci0: mem 0x42200000-0x4220ffff at device 16.1 numa-domain 0 on pci0 pcib0: Failed to translate resource 0-ffffffffffffffff type 3 for ahci0 ahci0: 0x10000 bytes of rid 0x18 res 3 failed (0, 0xffffffffffffffff). device_attach: ahci0 attach returned 6 acpi_syscontainer0: numa-domain 0 on acpi0 pcib16: numa-domain 1 on acpi0 pci16: numa-domain 1 on pcib16 pcib17: irq 282 at device 1.0 numa-domain 1 on pci16 pci17: numa-domain 1 on pcib17 pcib18: irq 283 at device 2.0 numa-domain 1 on pci16 pci18: numa-domain 1 on pcib18 pcib19: irq 284 at device 3.0 numa-domain 1 on pci16 pci19: numa-domain 1 on pcib19 pcib20: irq 285 at device 4.0 numa-domain 1 on pci16 pci20: numa-domain 1 on pcib20 pcib21: irq 286 at device 5.0 numa-domain 1 on pci16 pci21: numa-domain 1 on pcib21 pcib22: irq 287 at device 6.0 numa-domain 1 on pci16 pci22: numa-domain 1 on pcib22 pcib23: at device 7.0 numa-domain 1 on pci16 pci23: numa-domain 1 on pcib23 nvme0: mem 0x60000000-0x60003fff at device 0.0 numa-domain 1 on pci23 pcib24: irq 288 at device 8.0 numa-domain 1 on pci16 pci24: numa-domain 1 on pcib24 pcib25: irq 289 at device 9.0 numa-domain 1 on pci16 pci25: numa-domain 1 on pcib25 pcib26: irq 290 at device 10.0 numa-domain 1 on pci16 pci26: numa-domain 1 on pcib26 pcib27: irq 291 at device 11.0 numa-domain 1 on pci16 pci27: numa-domain 1 on pcib27 pcib28: irq 292 at device 12.0 numa-domain 1 on pci16 pci28: numa-domain 1 on pcib28 pcib29: irq 293 at device 13.0 numa-domain 1 on pci16 pci29: numa-domain 1 on pcib29 pcib30: irq 294 at device 14.0 numa-domain 1 on pci16 pci30: numa-domain 1 on pcib30 xhci2: mem 0x14000030000-0x1400003ffff,0x14000020000-0x1400002ffff at device 15.0 numa-domain 1 on pci16 xhci2: 64 bytes context size, 64-bit DMA usbus2 numa-domain 1 on xhci2 xhci3: mem 0x14000010000-0x1400001ffff,0x14000000000-0x1400000ffff at device 15.1 numa-domain 1 on pci16 xhci3: 64 bytes context size, 64-bit DMA usbus3 numa-domain 1 on xhci3 acpi_syscontainer1: numa-domain 1 on acpi0 acpi_tz0: on acpi0 acpi_syscontainer2: on acpi0 acpi_syscontainer3: on acpi0 acpi_syscontainer4: on acpi0 acpi_syscontainer5: on acpi0 acpi_syscontainer6: on acpi0 acpi_syscontainer7: on acpi0 acpi_syscontainer8: on acpi0 acpi_syscontainer9: on acpi0 acpi_syscontainer10: on acpi0 acpi_syscontainer11: on acpi0 acpi_syscontainer12: on acpi0 acpi_syscontainer13: on acpi0 acpi_syscontainer14: on acpi0 acpi_syscontainer15: on acpi0 acpi_syscontainer16: on acpi0 acpi_syscontainer17: on acpi0 acpi_syscontainer18: on acpi0 acpi_syscontainer19: on acpi0 acpi_syscontainer20: on acpi0 acpi_syscontainer21: on acpi0 acpi_syscontainer22: on acpi0 acpi_syscontainer23: on acpi0 acpi_syscontainer24: on acpi0 acpi_syscontainer25: on acpi0 acpi_syscontainer26: on acpi0 acpi_syscontainer27: on acpi0 acpi_syscontainer28: on acpi0 acpi_syscontainer29: on acpi0 acpi_syscontainer30: on acpi0 acpi_syscontainer31: on acpi0 acpi_syscontainer32: on acpi0 acpi_syscontainer33: on acpi0 uart0: iomem 0x402020000-0x40202ffff irq 5 numa-domain 0 on acpi0 uart0: console (115200,n,8,1) acpi_tz1: on acpi0 acpi_syscontainer34: on acpi0 acpi_syscontainer35: on acpi0 acpi_syscontainer36: on acpi0 acpi_syscontainer37: on acpi0 acpi_syscontainer38: on acpi0 acpi_syscontainer39: on acpi0 acpi_syscontainer40: on acpi0 acpi_syscontainer41: on acpi0 acpi_syscontainer42: on acpi0 acpi_syscontainer43: on acpi0 acpi_syscontainer44: on acpi0 acpi_syscontainer45: on acpi0 acpi_syscontainer46: on acpi0 acpi_syscontainer47: on acpi0 acpi_syscontainer48: on acpi0 acpi_syscontainer49: on acpi0 acpi_syscontainer50: on acpi0 acpi_syscontainer51: on acpi0 acpi_syscontainer52: on acpi0 acpi_syscontainer53: on acpi0 acpi_syscontainer54: on acpi0 acpi_syscontainer55: on acpi0 acpi_syscontainer56: on acpi0 acpi_syscontainer57: on acpi0 acpi_syscontainer58: on acpi0 acpi_syscontainer59: on acpi0 acpi_syscontainer60: on acpi0 acpi_syscontainer61: on acpi0 acpi_syscontainer62: on acpi0 acpi_syscontainer63: on acpi0 acpi_syscontainer64: on acpi0 acpi_syscontainer65: on acpi0 cpu0: on acpi0 acpi_tz2: on acpi0 acpi_tz3: on acpi0 acpi_tz4: on acpi0 acpi_tz5: on acpi0 acpi_tz6: on acpi0 acpi_tz7: on acpi0 acpi_tz8: on acpi0 acpi_tz9: on acpi0 acpi_tz10: on acpi0 acpi_tz11: on acpi0 acpi_tz12: on acpi0 acpi_tz13: on acpi0 acpi_tz14: on acpi0 acpi_tz15: on acpi0 acpi_tz16: on acpi0 acpi_tz17: on acpi0 acpi_tz18: on acpi0 acpi_tz19: on acpi0 acpi_tz20: on acpi0 acpi_tz21: on acpi0 acpi_tz22: on acpi0 acpi_tz23: on acpi0 acpi_tz24: on acpi0 acpi_tz25: on acpi0 acpi_tz26: on acpi0 acpi_tz27: on acpi0 acpi_tz28: on acpi0 acpi_tz29: on acpi0 acpi_tz30: on acpi0 acpi_tz31: on acpi0 acpi_tz32: on acpi0 acpi_tz33: on acpi0 acpi_tz34: on acpi0 acpi_tz35: on acpi0 acpi_tz36: on acpi0 acpi_tz37: on acpi0 acpi_tz38: on acpi0 acpi_tz39: on acpi0 acpi_tz40: on acpi0 acpi_tz41: on acpi0 acpi_tz42: on acpi0 acpi_tz43: on acpi0 acpi_tz44: on acpi0 acpi_tz45: on acpi0 acpi_tz46: on acpi0 acpi_tz47: on acpi0 acpi_tz48: on acpi0 acpi_tz49: on acpi0 acpi_tz50: on acpi0 acpi_tz51: on acpi0 acpi_tz52: on acpi0 acpi_tz53: on acpi0 acpi_tz54: on acpi0 acpi_tz55: on acpi0 acpi_tz56: on acpi0 acpi_tz57: on acpi0 acpi_tz58: on acpi0 acpi_tz59: on acpi0 acpi_tz60: on acpi0 acpi_tz61: on acpi0 acpi_tz62: on acpi0 acpi_tz63: on acpi0 acpi_tz64: on acpi0 acpi_tz65: on acpi0 armv8crypto0: Timecounters tick every 1.000 msec usbus0: 5.0Gbps Super Speed USB v3.0 usbus1: 5.0Gbps Super Speed USB v3.0 usbus2: 5.0Gbps Super Speed USB v3.0 usbus3: 5.0Gbps Super Speed USB v3.0 ugen0.1: <(0x14e4) XHCI root HUB> at usbus0 uhub0 numa-domain 0 on usbus0 uhub0: <(0x14e4) XHCI root HUB, class 9/0, rev 3.00/1.00, addr 1> on usbus0 ugen1.1: <(0x14e4) XHCI root HUB> at usbus1 uhub1 numa-domain 0 on usbus1 uhub1: <(0x14e4) XHCI root HUB, class 9/0, rev 3.00/1.00, addr 1> on usbus1 ugen2.1: <(0x14e4) XHCI root HUB> at usbus2 uhub2 numa-domain 1 on usbus2 uhub2: <(0x14e4) XHCI root HUB, class 9/0, rev 3.00/1.00, addr 1> on usbus2 ugen3.1: <(0x14e4) XHCI root HUB> at usbus3 uhub3 numa-domain 1 on usbus3 uhub3: <(0x14e4) XHCI root HUB, class 9/0, rev 3.00/1.00, addr 1> on usbus3 ahci0: mem 0x42220000-0x4222ffff at device 16.0 numa-domain 0 on pci0 pcib0: Failed to translate resource 0-ffffffffffffffff type 3 for ahci0 ahci0: 0x10000 bytes of rid 0x18 res 3 failed (0, 0xffffffffffffffff). device_attach: ahci0 attach returned 6 ahci0: mem 0x42200000-0x4220ffff at device 16.1 numa-domain 0 on pci0 pcib0: Failed to translate resource 0-ffffffffffffffff type 3 for ahci0 ahci0: 0x10000 bytes of rid 0x18 res 3 failed (0, 0xffffffffffffffff). device_attach: ahci0 attach returned 6 mlx5_core0: mem 0x10002000000-0x10003ffffff at device 0.0 numa-domain 0 on pci7 mlx5: Mellanox Core driver 3.7.1 (November 2021)uhub1: 2 ports with 2 removable, self powered uhub0: 2 ports with 2 removable, self powered uhub2: 2 ports with 2 removable, self powered uhub3: 2 ports with 2 removable, self powered ugen0.2: at usbus0 uhub4 numa-domain 0 on uhub0 uhub4: on usbus0 ugen1.2: at usbus1 uhub5 numa-domain 0 on uhub1 uhub5: <7-port Hub> on usbus1 mlx5_core0: INFO: mlx5_port_module_event:711:(pid 12): Module 0, status: plugged and enabled uhub4: 4 ports with 4 removable, self powered ugen0.3: at usbus0 uhub6 numa-domain 0 on uhub0 uhub6: on usbus0 uhub6: MTT enabled uhub5: 5 ports with 5 removable, self powered uhub6: 4 ports with 4 removable, self powered usb_msc_auto_quirk: UQ_MSC_NO_GETMAXLUN set for USB mass storage device American Megatrends Inc. Virtual Cdrom Device (0x046b:0xff20) ugen1.3: at usbus1 umass0 numa-domain 0 on uhub5 umass0: on usbus1 umass0: SCSI over Bulk-Only; quirks = 0x0100 umass0:2:0: Attached to scbus2 mlx5_core: INFO: (mlx5_core0): E-Switch: Total vports 9, l2 table size(65536), per vport: max uc(1024) max mc(16384) mlx5_core1: mem 0x10000000000-0x10001ffffff at device 0.1 numa-domain 0 on pci7 mpr0: Found device <81,End Device> <3.0Gbps> handle<0x000a> enclosureHandle<0x0002> slot 4 mpr0: At enclosure level 0 and connector name ( ) mpr0: Found device <81,End Device> <3.0Gbps> handle<0x000b> enclosureHandle<0x0002> slot 5 mpr0: At enclosure level 0 and connector name ( ) mpr0: Found device <81,End Device> <6.0Gbps> handle<0x000c> enclosureHandle<0x0002> slot 0 mpr0: At enclosure level 0 and connector name ( ) mpr0: Found device <81,End Device> <6.0Gbps> handle<0x000d> enclosureHandle<0x0002> slot 1 mpr0: At enclosure level 0 and connector name ( ) mpr0: Found device <81,End Device> <6.0Gbps> handle<0x000e> enclosureHandle<0x0002> slot 2 mpr0: At enclosure level 0 and connector name ( ) mpr0: Found device <81,End Device> <6.0Gbps> handle<0x000f> enclosureHandle<0x0002> slot 3 mpr0: At enclosure level 0 and connector name ( ) mpr0: Found device <4411,End Device> <12.0Gbps> handle<0x0010> enclosureHandle<0x0002> slot 16 mpr0: At enclosure level 0 and connector name ( ) mlx5_core1: INFO: mlx5_port_module_event:711:(pid 12): Module 1, status: plugged and enabled usb_msc_auto_quirk: UQ_MSC_NO_GETMAXLUN set for USB mass storage device American Megatrends Inc. Virtual HardDisk Device (0x046b:0xff31) usb_msc_auto_quirk: UQ_MSC_NO_TEST_UNIT_READY set for USB mass storage device American Megatrends Inc. Virtual HardDisk Device (0x046b:0xff31) usb_msc_auto_quirk: UQ_MSC_NO_START_STOP set for USB mass storage device American Megatrends Inc. Virtual HardDisk Device (0x046b:0xff31) ugen1.4: at usbus1 umass1 numa-domain 0 on uhub5 umass1: on usbus1 umass1: SCSI over Bulk-Only; quirks = 0x0105 umass1:3:1: Attached to scbus3 ugen1.5: at usbus1 ugen1.6: at usbus1 ukbd0 numa-domain 0 on uhub5 ukbd0: on usbus1 kbd1 at ukbd0 mlx5_core: INFO: (mlx5_core1): E-Switch: Total vports 9, l2 table size(65536), per vport: max uc(1024) max mc(16384) mce0: Ethernet address: 0c:42:a1:e3:84:a4 mce0: link state changed to DOWN nda0 at nvme0 bus 0 scbus1 target 0 lun 1 nda0: da0 at mpr0 bus 0 scbus0 target 10 lun 0 da0: Fixed Direct Access SPC-4 SCSI device da0: Serial Number WD-WCC132264667 da0: 600.000MB/s transfers da0: Command Queueing enabled da0: 3815447MB (7814037168 512 byte sectors) da1 at mpr0 bus 0 scbus0 target 11 lun 0 da1: Fixed Direct Access SPC-4 SCSI device da1: Serial Number WD-WMC130D6TSL2 da1: 600.000MB/s transfers da1: Command Queueing enabled da1: 3815447MB (7814037168 512 byte sectors) da4 at mpr0 bus 0 scbus0 target 19 lun 0 da4: Fixed Direct Access SPC-4 SCSI device da4: Serial Number WD-WCC132248884 da4: 600.000MB/s transfers da4: Command Queueing enabled da4: 3815447MB (7814037168 512 byte sectors) da5 at mpr0 bus 0 scbus0 target 20 lun 0 da5: Fixed Direct Access SPC-4 SCSI device da5: Serial Number WD-WCC132261529 da5: 600.000MB/s transfers da5: Command Queueing enabled da5: 3815447MB (7814037168 512 byte sectors) da2 at mpr0 bus 0 scbus0 target 17 lun 0 da2: Fixed Direct Access SPC-4 SCSI device da2: Serial Number WD-WCATR2406302 da2: 300.000MB/s transfers da2: Command Queueing enabled da2: 476940MB (976773168 512 byte sectors) da3 at mpr0 bus 0 scbus0 target 18 lun 0 da3: Fixed Direct Access SPC-4 SCSI device da3: Serial Number WD-WCATR2385783 da3: 300.000MB/s transfers da3: Command Queueing enabled da3: 476940MB (976773168 512 byte sectors) nda0: Serial Number S3ESNX0J910972T nda0: nvme version 1.2 x4 (max x4) lanes PCIe Gen3 (max Gen3) link nda0: 238475MB (488397168 512 byte sectors) pass2 at mpr0 bus 0 scbus0 target 12 lun 0 pass2: Fixed Enclosure Services SPC-3 SCSI device pass2: 1200.000MB/s transfers pass2: Command Queueing enabled cd0 at umass-sim0 bus 0 scbus2 target 0 lun 0 cd0: Removable CD-ROM SCSI device cd0: Serial Number AAAABBBBCCCC1 cd0: 40.000MB/s transfers cd0: Attempt to query device size failed: NOT READY, Medium not present cd0: quirks=0x10<10_BYTE_ONLY> da6 at umass-sim1 bus 1 scbus3 target 0 lun 0 da6: Removable Direct Access SCSI device da6: Serial Number AAAABBBBCCCC3 da6: 40.000MB/s transfers da6: Attempt to query device size failed: NOT READY, Medium not present da6: quirks=0x2 mce1: Ethernet address: 0c:42:a1:e3:84:a5 mce1: link state changed to DOWN CPU 0: Cavium ThunderX2 r1p2 affinity: 0 0 0 Cache Type = <64 byte D-cacheline,64 byte I-cacheline,PIPT ICache,64 byte ERG,64 byte CWG> Instruction Set Attributes 0 = Instruction Set Attributes 1 = <> Trying to mount root from ufs:/dev/nda0p2 [rw]... Processor Features 0 = Processor Features 1 = <> Memory Model Features 0 = Memory Model Features 1 = Memory Model Features 2 = <32bit CCIDX,48bit VA> Debug Features 0 = Debug Features 1 = <> Auxiliary Features 0 = <> Auxiliary Features 1 = <> AArch32 Instruction Set Attributes 5 = <> AArch32 Media and VFP Features 0 = <> AArch32 Media and VFP Features 1 = <> CPU 1: Cavium ThunderX2 r1p2 affinity: 0 1 0 CPU 2: Cavium ThunderX2 r1p2 affinity: 0 2 0 CPU 3: Cavium ThunderX2 r1p2 affinity: 0 3 0 CPU 4: Cavium ThunderX2 r1p2 affinity: 0 4 0 CPU 5: Cavium ThunderX2 r1p2 affinity: 0 5 0 CPU 6: Cavium ThunderX2 r1p2 affinity: 0 6 0 CPU 7: Cavium ThunderX2 r1p2 affinity: 0 7 0 CPU 8: Cavium ThunderX2 r1p2 affinity: 0 8 0 CPU 9: Cavium ThunderX2 r1p2 affinity: 0 9 0 CPU 10: Cavium ThunderX2 r1p2 affinity: 0 10 0 CPU 11: Cavium ThunderX2 r1p2 affinity: 0 11 0 CPU 12: Cavium ThunderX2 r1p2 affinity: 0 12 0 CPU 13: Cavium ThunderX2 r1p2 affinity: 0 13 0 CPU 14: Cavium ThunderX2 r1p2 affinity: 0 14 0 CPU 15: Cavium ThunderX2 r1p2 affinity: 0 15 0 CPU 16: Cavium ThunderX2 r1p2 affinity: 0 16 0 CPU 17: Cavium ThunderX2 r1p2 affinity: 0 17 0 CPU 18: Cavium ThunderX2 r1p2 affinity: 0 18 0 CPU 19: Cavium ThunderX2 r1p2 affinity: 0 19 0 CPU 20: Cavium ThunderX2 r1p2 affinity: 0 20 0 CPU 21: Cavium ThunderX2 r1p2 affinity: 0 21 0 CPU 22: Cavium ThunderX2 r1p2 affinity: 0 22 0 CPU 23: Cavium ThunderX2 r1p2 affinity: 0 23 0 CPU 24: Cavium ThunderX2 r1p2 affinity: 0 24 0 CPU 25: Cavium ThunderX2 r1p2 affinity: 0 25 0 CPU 26: Cavium ThunderX2 r1p2 affinity: 0 26 0 CPU 27: Cavium ThunderX2 r1p2 affinity: 0 27 0 CPU 28: Cavium ThunderX2 r1p2 affinity: 0 28 0 CPU 29: Cavium ThunderX2 r1p2 affinity: 0 29 0 CPU 30: Cavium ThunderX2 r1p2 affinity: 0 30 0 CPU 31: Cavium ThunderX2 r1p2 affinity: 0 31 0 CPU 32: Cavium ThunderX2 r1p2 affinity: 0 0 1 CPU 33: Cavium ThunderX2 r1p2 affinity: 0 1 1 CPU 34: Cavium ThunderX2 r1p2 affinity: 0 2 1 CPU 35: Cavium ThunderX2 r1p2 affinity: 0 3 1 CPU 36: Cavium ThunderX2 r1p2 affinity: 0 4 1 CPU 37: Cavium ThunderX2 r1p2 affinity: 0 5 1 CPU 38: Cavium ThunderX2 r1p2 affinity: 0 6 1 CPU 39: Cavium ThunderX2 r1p2 affinity: 0 7 1 CPU 40: Cavium ThunderX2 r1p2 affinity: 0 8 1 CPU 41: Cavium ThunderX2 r1p2 affinity: 0 9 1 CPU 42: Cavium ThunderX2 r1p2 affinity: 0 10 1 CPU 43: Cavium ThunderX2 r1p2 affinity: 0 11 1 CPU 44: Cavium ThunderX2 r1p2 affinity: 0 12 1 CPU 45: Cavium ThunderX2 r1p2 affinity: 0 13 1 CPU 46: Cavium ThunderX2 r1p2 affinity: 0 14 1 CPU 47: Cavium ThunderX2 r1p2 affinity: 0 15 1 CPU 48: Cavium ThunderX2 r1p2 affinity: 0 16 1 CPU 49: Cavium ThunderX2 r1p2 affinity: 0 17 1 CPU 50: Cavium ThunderX2 r1p2 affinity: 0 18 1 CPU 51: Cavium ThunderX2 r1p2 affinity: 0 19 1 CPU 52: Cavium ThunderX2 r1p2 affinity: 0 20 1 CPU 53: Cavium ThunderX2 r1p2 affinity: 0 21 1 CPU 54: Cavium ThunderX2 r1p2 affinity: 0 22 1 CPU 55: Cavium ThunderX2 r1p2 affinity: 0 23 1 CPU 56: Cavium ThunderX2 r1p2 affinity: 0 24 1 CPU 57: Cavium ThunderX2 r1p2 affinity: 0 25 1 CPU 58: Cavium ThunderX2 r1p2 affinity: 0 26 1 CPU 59: Cavium ThunderX2 r1p2 affinity: 0 27 1 CPU 60: Cavium ThunderX2 r1p2 affinity: 0 28 1 CPU 61: Cavium ThunderX2 r1p2 affinity: 0 29 1 CPU 62: Cavium ThunderX2 r1p2 affinity: 0 30 1 CPU 63: Cavium ThunderX2 r1p2 affinity: 0 31 1 CPU 64: Cavium ThunderX2 r1p2 affinity: 0 0 2 CPU 65: Cavium ThunderX2 r1p2 affinity: 0 1 2 CPU 66: Cavium ThunderX2 r1p2 affinity: 0 2 2 CPU 67: Cavium ThunderX2 r1p2 affinity: 0 3 2 CPU 68: Cavium ThunderX2 r1p2 affinity: 0 4 2 CPU 69: Cavium ThunderX2 r1p2 affinity: 0 5 2 CPU 70: Cavium ThunderX2 r1p2 affinity: 0 6 2 CPU 71: Cavium ThunderX2 r1p2 affinity: 0 7 2 CPU 72: Cavium ThunderX2 r1p2 affinity: 0 8 2 CPU 73: Cavium ThunderX2 r1p2 affinity: 0 9 2 CPU 74: Cavium ThunderX2 r1p2 affinity: 0 10 2 CPU 75: Cavium ThunderX2 r1p2 affinity: 0 11 2 CPU 76: Cavium ThunderX2 r1p2 affinity: 0 12 2 CPU 77: Cavium ThunderX2 r1p2 affinity: 0 13 2 CPU 78: Cavium ThunderX2 r1p2 affinity: 0 14 2 CPU 79: Cavium ThunderX2 r1p2 affinity: 0 15 2 CPU 80: Cavium ThunderX2 r1p2 affinity: 0 16 2 CPU 81: Cavium ThunderX2 r1p2 affinity: 0 17 2 CPU 82: Cavium ThunderX2 r1p2 affinity: 0 18 2 CPU 83: Cavium ThunderX2 r1p2 affinity: 0 19 2 CPU 84: Cavium ThunderX2 r1p2 affinity: 0 20 2 CPU 85: Cavium ThunderX2 r1p2 affinity: 0 21 2 CPU 86: Cavium ThunderX2 r1p2 affinity: 0 22 2 CPU 87: Cavium ThunderX2 r1p2 affinity: 0 23 2 CPU 88: Cavium ThunderX2 r1p2 affinity: 0 24 2 CPU 89: Cavium ThunderX2 r1p2 affinity: 0 25 2 CPU 90: Cavium ThunderX2 r1p2 affinity: 0 26 2 CPU 91: Cavium ThunderX2 r1p2 affinity: 0 27 2 CPU 92: Cavium ThunderX2 r1p2 affinity: 0 28 2 CPU 93: Cavium ThunderX2 r1p2 affinity: 0 29 2 CPU 94: Cavium ThunderX2 r1p2 affinity: 0 30 2 CPU 95: Cavium ThunderX2 r1p2 affinity: 0 31 2 CPU 96: Cavium ThunderX2 r1p2 affinity: 0 0 3 CPU 97: Cavium ThunderX2 r1p2 affinity: 0 1 3 CPU 98: Cavium ThunderX2 r1p2 affinity: 0 2 3 CPU 99: Cavium ThunderX2 r1p2 affinity: 0 3 3 CPU100: Cavium ThunderX2 r1p2 affinity: 0 4 3 CPU101: Cavium ThunderX2 r1p2 affinity: 0 5 3 CPU102: Cavium ThunderX2 r1p2 affinity: 0 6 3 CPU103: Cavium ThunderX2 r1p2 affinity: 0 7 3 CPU104: Cavium ThunderX2 r1p2 affinity: 0 8 3 CPU105: Cavium ThunderX2 r1p2 affinity: 0 9 3 CPU106: Cavium ThunderX2 r1p2 affinity: 0 10 3 CPU107: Cavium ThunderX2 r1p2 affinity: 0 11 3 CPU108: Cavium ThunderX2 r1p2 affinity: 0 12 3 CPU109: Cavium ThunderX2 r1p2 affinity: 0 13 3 CPU110: Cavium ThunderX2 r1p2 affinity: 0 14 3 CPU111: Cavium ThunderX2 r1p2 affinity: 0 15 3 CPU112: Cavium ThunderX2 r1p2 affinity: 0 16 3 CPU113: Cavium ThunderX2 r1p2 affinity: 0 17 3 CPU114: Cavium ThunderX2 r1p2 affinity: 0 18 3 CPU115: Cavium ThunderX2 r1p2 affinity: 0 19 3 CPU116: Cavium ThunderX2 r1p2 affinity: 0 20 3 CPU117: Cavium ThunderX2 r1p2 affinity: 0 21 3 CPU118: Cavium ThunderX2 r1p2 affinity: 0 22 3 CPU119: Cavium ThunderX2 r1p2 affinity: 0 23 3 CPU120: Cavium ThunderX2 r1p2 affinity: 0 24 3 CPU121: Cavium ThunderX2 r1p2 affinity: 0 25 3 CPU122: Cavium ThunderX2 r1p2 affinity: 0 26 3 CPU123: Cavium ThunderX2 r1p2 affinity: 0 27 3 CPU124: Cavium ThunderX2 r1p2 affinity: 0 28 3 CPU125: Cavium ThunderX2 r1p2 affinity: 0 29 3 CPU126: Cavium ThunderX2 r1p2 affinity: 0 30 3 CPU127: Cavium ThunderX2 r1p2 affinity: 0 31 3 CPU128: Cavium ThunderX2 r1p2 affinity: 1 0 0 CPU129: Cavium ThunderX2 r1p2 affinity: 1 1 0 CPU130: Cavium ThunderX2 r1p2 affinity: 1 2 0 CPU131: Cavium ThunderX2 r1p2 affinity: 1 3 0 CPU132: Cavium ThunderX2 r1p2 affinity: 1 4 0 CPU133: Cavium ThunderX2 r1p2 affinity: 1 5 0 CPU134: Cavium ThunderX2 r1p2 affinity: 1 6 0 CPU135: Cavium ThunderX2 r1p2 affinity: 1 7 0 CPU136: Cavium ThunderX2 r1p2 affinity: 1 8 0 CPU137: Cavium ThunderX2 r1p2 affinity: 1 9 0 CPU138: Cavium ThunderX2 r1p2 affinity: 1 10 0 CPU139: Cavium ThunderX2 r1p2 affinity: 1 11 0 CPU140: Cavium ThunderX2 r1p2 affinity: 1 12 0 CPU141: Cavium ThunderX2 r1p2 affinity: 1 13 0 CPU142: Cavium ThunderX2 r1p2 affinity: 1 14 0 CPU143: Cavium ThunderX2 r1p2 affinity: 1 15 0 CPU144: Cavium ThunderX2 r1p2 affinity: 1 16 0 CPU145: Cavium ThunderX2 r1p2 affinity: 1 17 0 CPU146: Cavium ThunderX2 r1p2 affinity: 1 18 0 CPU147: Cavium ThunderX2 r1p2 affinity: 1 19 0 CPU148: Cavium ThunderX2 r1p2 affinity: 1 20 0 CPU149: Cavium ThunderX2 r1p2 affinity: 1 21 0 CPU150: Cavium ThunderX2 r1p2 affinity: 1 22 0 CPU151: Cavium ThunderX2 r1p2 affinity: 1 23 0 CPU152: Cavium ThunderX2 r1p2 affinity: 1 24 0 CPU153: Cavium ThunderX2 r1p2 affinity: 1 25 0 CPU154: Cavium ThunderX2 r1p2 affinity: 1 26 0 CPU155: Cavium ThunderX2 r1p2 affinity: 1 27 0 CPU156: Cavium ThunderX2 r1p2 affinity: 1 28 0 CPU157: Cavium ThunderX2 r1p2 affinity: 1 29 0 CPU158: Cavium ThunderX2 r1p2 affinity: 1 30 0 CPU159: Cavium ThunderX2 r1p2 affinity: 1 31 0 CPU160: Cavium ThunderX2 r1p2 affinity: 1 0 1 CPU161: Cavium ThunderX2 r1p2 affinity: 1 1 1 CPU162: Cavium ThunderX2 r1p2 affinity: 1 2 1 CPU163: Cavium ThunderX2 r1p2 affinity: 1 3 1 CPU164: Cavium ThunderX2 r1p2 affinity: 1 4 1 CPU165: Cavium ThunderX2 r1p2 affinity: 1 5 1 CPU166: Cavium ThunderX2 r1p2 affinity: 1 6 1 CPU167: Cavium ThunderX2 r1p2 affinity: 1 7 1 CPU168: Cavium ThunderX2 r1p2 affinity: 1 8 1 CPU169: Cavium ThunderX2 r1p2 affinity: 1 9 1 CPU170: Cavium ThunderX2 r1p2 affinity: 1 10 1 CPU171: Cavium ThunderX2 r1p2 affinity: 1 11 1 CPU172: Cavium ThunderX2 r1p2 affinity: 1 12 1 CPU173: Cavium ThunderX2 r1p2 affinity: 1 13 1 CPU174: Cavium ThunderX2 r1p2 affinity: 1 14 1 CPU175: Cavium ThunderX2 r1p2 affinity: 1 15 1 CPU176: Cavium ThunderX2 r1p2 affinity: 1 16 1 CPU177: Cavium ThunderX2 r1p2 affinity: 1 17 1 CPU178: Cavium ThunderX2 r1p2 affinity: 1 18 1 CPU179: Cavium ThunderX2 r1p2 affinity: 1 19 1 CPU180: Cavium ThunderX2 r1p2 affinity: 1 20 1 CPU181: Cavium ThunderX2 r1p2 affinity: 1 21 1 CPU182: Cavium ThunderX2 r1p2 affinity: 1 22 1 CPU183: Cavium ThunderX2 r1p2 affinity: 1 23 1 CPU184: Cavium ThunderX2 r1p2 affinity: 1 24 1 CPU185: Cavium ThunderX2 r1p2 affinity: 1 25 1 CPU186: Cavium ThunderX2 r1p2 affinity: 1 26 1 CPU187: Cavium ThunderX2 r1p2 affinity: 1 27 1 CPU188: Cavium ThunderX2 r1p2 affinity: 1 28 1 CPU189: Cavium ThunderX2 r1p2 affinity: 1 29 1 CPU190: Cavium ThunderX2 r1p2 affinity: 1 30 1 CPU191: Cavium ThunderX2 r1p2 affinity: 1 31 1 CPU192: Cavium ThunderX2 r1p2 affinity: 1 0 2 CPU193: Cavium ThunderX2 r1p2 affinity: 1 1 2 CPU194: Cavium ThunderX2 r1p2 affinity: 1 2 2 CPU195: Cavium ThunderX2 r1p2 affinity: 1 3 2 CPU196: Cavium ThunderX2 r1p2 affinity: 1 4 2 CPU197: Cavium ThunderX2 r1p2 affinity: 1 5 2 CPU198: Cavium ThunderX2 r1p2 affinity: 1 6 2 CPU199: Cavium ThunderX2 r1p2 affinity: 1 7 2 CPU200: Cavium ThunderX2 r1p2 affinity: 1 8 2 CPU201: Cavium ThunderX2 r1p2 affinity: 1 9 2 CPU202: Cavium ThunderX2 r1p2 affinity: 1 10 2 CPU203: Cavium ThunderX2 r1p2 affinity: 1 11 2 CPU204: Cavium ThunderX2 r1p2 affinity: 1 12 2 CPU205: Cavium ThunderX2 r1p2 affinity: 1 13 2 CPU206: Cavium ThunderX2 r1p2 affinity: 1 14 2 CPU207: Cavium ThunderX2 r1p2 affinity: 1 15 2 CPU208: Cavium ThunderX2 r1p2 affinity: 1 16 2 CPU209: Cavium ThunderX2 r1p2 affinity: 1 17 2 CPU210: Cavium ThunderX2 r1p2 affinity: 1 18 2 CPU211: Cavium ThunderX2 r1p2 affinity: 1 19 2 CPU212: Cavium ThunderX2 r1p2 affinity: 1 20 2 CPU213: Cavium ThunderX2 r1p2 affinity: 1 21 2 CPU214: Cavium ThunderX2 r1p2 affinity: 1 22 2 CPU215: Cavium ThunderX2 r1p2 affinity: 1 23 2 CPU216: Cavium ThunderX2 r1p2 affinity: 1 24 2 CPU217: Cavium ThunderX2 r1p2 affinity: 1 25 2 CPU218: Cavium ThunderX2 r1p2 affinity: 1 26 2 CPU219: Cavium ThunderX2 r1p2 affinity: 1 27 2 CPU220: Cavium ThunderX2 r1p2 affinity: 1 28 2 CPU221: Cavium ThunderX2 r1p2 affinity: 1 29 2 CPU222: Cavium ThunderX2 r1p2 affinity: 1 30 2 CPU223: Cavium ThunderX2 r1p2 affinity: 1 31 2 CPU224: Cavium ThunderX2 r1p2 affinity: 1 0 3 CPU225: Cavium ThunderX2 r1p2 affinity: 1 1 3 CPU226: Cavium ThunderX2 r1p2 affinity: 1 2 3 CPU227: Cavium ThunderX2 r1p2 affinity: 1 3 3 CPU228: Cavium ThunderX2 r1p2 affinity: 1 4 3 CPU229: Cavium ThunderX2 r1p2 affinity: 1 5 3 CPU230: Cavium ThunderX2 r1p2 affinity: 1 6 3 CPU231: Cavium ThunderX2 r1p2 affinity: 1 7 3 CPU232: Cavium ThunderX2 r1p2 affinity: 1 8 3 CPU233: Cavium ThunderX2 r1p2 affinity: 1 9 3 CPU234: Cavium ThunderX2 r1p2 affinity: 1 10 3 CPU235: Cavium ThunderX2 r1p2 affinity: 1 11 3 CPU236: Cavium ThunderX2 r1p2 affinity: 1 12 3 CPU237: Cavium ThunderX2 r1p2 affinity: 1 13 3 CPU238: Cavium ThunderX2 r1p2 affinity: 1 14 3 CPU239: Cavium ThunderX2 r1p2 affinity: 1 15 3 CPU240: Cavium ThunderX2 r1p2 affinity: 1 16 3 CPU241: Cavium ThunderX2 r1p2 affinity: 1 17 3 CPU242: Cavium ThunderX2 r1p2 affinity: 1 18 3 CPU243: Cavium ThunderX2 r1p2 affinity: 1 19 3 CPU244: Cavium ThunderX2 r1p2 affinity: 1 20 3 CPU245: Cavium ThunderX2 r1p2 affinity: 1 21 3 CPU246: Cavium ThunderX2 r1p2 affinity: 1 22 3 CPU247: Cavium ThunderX2 r1p2 affinity: 1 23 3 CPU248: Cavium ThunderX2 r1p2 affinity: 1 24 3 CPU249: Cavium ThunderX2 r1p2 affinity: 1 25 3 CPU250: Cavium ThunderX2 r1p2 affinity: 1 26 3 CPU251: Cavium ThunderX2 r1p2 affinity: 1 27 3 CPU252: Cavium ThunderX2 r1p2 affinity: 1 28 3 CPU253: Cavium ThunderX2 r1p2 affinity: 1 29 3 CPU254: Cavium ThunderX2 r1p2 affinity: 1 30 3 CPU255: Cavium ThunderX2 r1p2 affinity: 1 31 3 Release APs...done TCP_ratelimit: Is now initialized WARNING: WITNESS option enabled, expect reduced performance. WARNING: / was not properly dismounted WARNING: /: mount pending error: blocks 16 files 0 Dual Console: Video Primary, Serial Secondary lo0: link state changed to UP mce0: link state changed to UP mce1: link state changed to UP mce1: link state changed to DOWN mce1: link state changed to UP